Abstract: The present invention discloses a method for preparing a nano-scale field-effect transistor, and belongs to the field of large-scale integrated circuit manufacturing technologies. The method focuses on preparing a nano-scale field-effect transistor on an SOI substrate by epitaxial growth. In the invention, the material and appearance of a channel of a nano-scale device may be accurately controlled by using an epitaxy process, and the device performance may be further optimized; moreover, a threshold voltage may be flexibly adjusted to adapt for requirements of different IC designs by realizing different channel doping types and doping concentrations; also, a gate structure with a consistent width in a height direction may be obtained, the parasitism and fluctuation of the device may be reduced, and at the same time, the method can be well compatible with CMOS post-gate processes, and is simple in procedure and low in cost.

Abstract: The present invention discloses a method for fabricating a quasi SOI source-drain multi-gate device, belonging to a field of manufacturing ultra large scale integrated circuit, the method comprises in sequence the following steps of: forming a Fin strip-shaped active region on a first semiconductor substrate; forming a STI isolation layer; depositing a gate dielectric layer and a gate material layer, forming a gate stack structure; forming a doped structure of a source-drain extension region; forming a recessed source-drain structure; forming a quasi SOI source-drain isolation layer; in-situ doping an epitaxial source and drain of a second semiconductor material and performing annealing for activating; removing a dummy gate and performing a deposition of a high k metal gate again; and forming a contact and a metal interconnection.

Abstract: A method for fabricating multiple layers of ultra narrow silicon wires comprises the steps of fabricating wet-etch masking layers of silicon; forming a Fin and source/drain regions located at both ends thereof by epitaxy; forming the multiple layers of ultra narrow silicon wires. The present invention has advantages in that: the atom layer depositing may define the position of the ultra narrow silicon wires accurately, having a good controllability; the anisotropic wet-etch for silicon is performed in a self-stop manner and has a large process window, so that the cross-section shape of the nanowires formed by wet-etch is uniform and smooth.

Abstract: Disclosed is a semiconductor structure, comprising: a semiconductor substrate and multilayer superfine silicon lines, wherein a profile shape of each of the multilayer superfine silicon lines is controlled dually by a crystal orientation of the substrate and an axial crystal orientation of the line. Also disclosed is a method of forming the same comprises: forming a fin-shaped silicon island (Fin) and a source-drain region on the two ends thereof via an etching process; preparing a corrosion shielding layer for silicon; and forming multilayer superfine silicon lines. The invention has the following advantages: the locations and the sectional shapes of the multilayer superfine silicon lines finally formed are uniform and controllable; the anisotropic corrosion for silicon stop automatically, the process window is large, and silicon lines with different diameters may be achieved from the same silicon wafer.

Abstract: A method for preparing a multilayer superfine silicon line, comprising: preparing an etching masking layer of silicon; forming a fin and source/drain region on both ends thereof by epitaxy; and forming a multilayer superfine silicon line. The method has the following advantages: the atom layer deposition accurately defines the position of the superfine line, giving good controllability; the anisotropic etching of the silicon is automatically stopped, so the process window is large, and the cross section of a nanowire obtained via etching is uniform and flat; a method of mask preparation before channel epitaxy is employed to provide a simple process of forming a multilayer sidewall etching mask, i.e., the multilayer sidewall mask is obtained by etching an epitaxial window only once irrespective of the number of masking layers; a line having a size less than 10 nm can be prepared in conjunction with oxidation technology, thus satisfying the requirement of the key process of a small-sized device.

Abstract: The present invention discloses a method for fabricating a quasi-SOI source/drain field effect transistor device, which comprises the steps of forming an active region of the device; forming a gate stack structure of the device; doping a source/drain extension region, and forming a first layer of side wall at two sides of the gate stack structure; forming a recessed source/drain structure; forming a quasi-SOI source/drain isolation layer; in-situ doping an epitaxial second semiconductor material source/drain, and activating by annealing; removing the previous dummy gate and re-depositing a high-k metal gate, if a post-gate process is employed; and forming contacts and metal interconnections.

Abstract: The present invention discloses a method for fabricating a quasi-SOI source/drain field effect transistor device, which comprises the steps of forming an active region of the device; forming a gate stack structure of the device; doping a source/drain extension region, and forming a first layer of side wall at two sides of the gate stack structure; forming a recessed source/drain structure; forming a quasi-SOI source/drain isolation layer; in-situ doping an epitaxial second semiconductor material source/drain, and activating by annealing; removing the previous dummy gate and re-depositing a high-k metal gate, if a post-gate process is employed; and forming contacts and metal interconnections.