Abstract: Method for fabricating semiconductor devices with high-K materials without the presence of undesired formations of the high-K material. A preferred embodiment comprises forming a layer of material over a layer of a high-K material, etching the layer of material to expose a portion of the high-K material, performing a CDE (Chemical Downstream Etch) to remove any residual material formed during the etching, and etching the layer of the high-K material into alignment with remaining portions of the layer of material. The removal of the residual material results in a predictable trimming of the high-K material so that the semiconductor device has predictable and consistent performance, which is not possible if the high-K material has unpredictable dimensions.

Abstract: Semiconductor devices and methods of manufacturing thereof are disclosed. A plurality of features is formed on a workpiece, the plurality of features being located in a first region and a second region of the workpiece. Features in the first region have a first lateral dimension, and features in the second region have a second lateral dimension, wherein the second lateral dimension is greater than the first lateral dimension. The first region is masked, and the second lateral dimension of features in the second region is reduced.

Abstract: Integrated circuit transistors may be fabricated by simultaneously removing a photoresist layer on a first active area of an integrated circuit substrate and a carbon-containing layer on a second active area of the integrated circuit substrate, to expose a nitride stress-generating layer on the second active area. A single mask may be used to define the second active area for removal of the photoresist layer on the first active area and for implanting source/drain regions into the second active area.

Abstract: A method for manufacturing a semiconductor device including a substrate to be processed having a conductive layer essentially consisting of platinum includes etching the conductive layer, and generating plasma and cleaning the substrate, to which an etching product adhere, by means of ions in the plasma. The cleaning includes heating the substrate to a first temperature, introducing gas, which contains chlorine and nitrogen and in which a ratio of chlorine atoms to nitrogen atoms is 9:1 to 5:5, and applying high-frequency power to an electrode, on which the substrate is placed.

Abstract: A method of etching a ferroelectric device 100 having a ferroelectric layer 112 between a top and a bottom electrode 114, 108 is disclosed herein. Hardmasks 116, 118 are deposited on the top electrode 114, two or more hardmasks being spaced apart by narrow first regions 115 and spaced apart from other hardmasks by wider second regions 117. The top electrode 114 and ferroelectric layer 112 are then etched to pattern the top electrode 114 thus forming capacitors 102, 104, and the bottom electrode 108 is etched by a process in which the second regions are etched more slowly than the second regions. Those capacitors having a first region between them have a common bottom electrode 108, but in the second regions the bottom electrode is severed. To pattern the bottom electrode 108, a fluorine-based chemistry followed thereafter by a CO-based chemistry are used in a two step etching process.

Abstract: A ferroelectric capacitor device comprises a substrate, a contact plug passing through the substrate, a first electrode formed on the substrate, the first electrode being electrically connected to said plug, a ferroelectric layer formed on the first electrode, a second electrode formed on the ferroelectric layer, one or more first encapsulation layers on the second electrode, the encapsulation layers extending over the device, and one or more hydrogen storage material layers on the encapsulation layers. One or more second encapsulation layers may be formed on the one or more hydrogen storage material layers.

Abstract: The present invention provides a ferroelectric device relatively free of fences by using a hardmask having high etching selectivity relative to an underlying barrier layer. The present invention also includes a method for suppressing the fences clinging to the sidewalls of ferroelectric devices. Additionally, the present invention provides a ferroelectric device having a hardmask relatively thin compared to an underlying barrier layer when compared to prior art devices.

Abstract: The present invention provides a sidewall oxygen diffusion barrier and a method for fabricating the sidewall oxygen diffusion barrier that reduces the diffusion of oxygen into contact plugs during a CW hole reactive ion etch of a ferroelectric capacitor of an FeRAM device. In one embodiment the sidewall barrier is formed from a substrate fence. In another embodiment, the sidewall barrier is formed by etching back an oxygen barrier.

Abstract: A device and method for forming a capacitor device comprises forming a substrate, forming a first interlayer dielectric layer on the substrate and forming two or more contact plugs through the substrate. A conducting layer is formed on the first interlayer dielectric layer and an electrode is formed on alternate ones of the contact plugs by etching the conducting layer. The etched electrodes are then coated with a ferroelectric layer. The ferroelectric layer is etched from the surfaces separating the contact plugs and additional electrodes are created by filling the spaces between the electrodes on alternate ones of the contact plugs with a conductive material to establish electrical contact between the plugs and the electrodes.

Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a capacitor provided above the semiconductor substrate and including a bottom electrode, a dielectric film provided on the bottom electrode, and a top electrode provided on the dielectric film, a mask film provided on the top electrode and used as a mask when a pattern of the capacitor is formed, wherein an inclination of a side surface of the mask film is gentler than an inclination of a side surface of the top electrode and an inclination of a side surface of the dielectric film.

Abstract: An Iridium barrier layer is between a contact plug and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode and barrier layer using a fluorine-based recipe resulting in the formation of a first fence clinging to the sidewalls. Next the remaining barrier layer is etched using a CO-based recipe. A second fence is formed clinging to and structurally supported by the first fence. At the same time, the CO-based recipe etches away a substantial portion of the first fence to remove the structural support provided to the second fence. The second fence is therefore lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences. The etched barrier layer has a sidewall transition. The sidewalls have a relatively low taper angle above the sidewall transition and a relatively steep taper angle below the sidewall transition.

Abstract: A method for fabricating a device and a device, such as a ferroelectric capacitor, having a substrate, a contact plug through the substrate, a first barrier layer on the substrate, a first electrode on the first barrier layer, a dielectric layer on the first electrode, and a second electrode on the dielectric layer, comprises etching the second electrode and the dielectric layer of the device using a first hardmask, to shape the second electrode and the dielectric layer. The first hardmask is then removed and one or more encapsulating layers are applied to the second electrode and the dielectric layer. A further hardmask is applied to the one or more encapsulating layers. The first electrode is then etched according to the second hardmask down to the first barrier layer and the second hardmask is then removed from the one or more encapsulating layers.

Abstract: A ferroelectric device includes a bottom electrode on which are formed ferrocapacitor elements and, over the ferroelectric elements, top electrodes. The bottom electrodes are connected to lower layers of the device via conductive plugs, and the plugs and bottom electrodes are spaced apart by barrier elements of Ir and/or IrO2. The barrier elements are narrower than the bottom electrode elements, and are formed by a separate etching process. This means that Ir fences are not formed during the etching of the bottom electrode. Also, little Ir and/or IrO2 diffuses through the bottom electrode to the ferroelectric elements, and therefore there is little risk of damage to the ferroelectric material.

Abstract: A method for manufacturing a semiconductor device including a substrate to be processed having a conductive layer essentially consisting of platinum includes etching the conductive layer, and generating plasma and cleaning the substrate, to which an etching product adhere, by means of ions in the plasma. The cleaning includes heating the substrate to a first temperature, introducing gas, which contains chlorine and nitrogen and in which a ratio of chlorine atoms to nitrogen atoms is 9:1 to 5:5, and applying high-frequency power to an electrode, on which the substrate is placed.

Abstract: A ferroelectric capacitor device, such as an FeRAM device is formed by forming a substrate extending in a first plane and comprising a number of layers of material, forming a hard mask layer on the substrate and forming a first layer of a first material on the hard mask layer. The hard mask shape is then defined by etching the hard mask layer. A second layer of the first material is deposited on the etched hard mask layer. The deposited second layer has one or more side surfaces extending substantially perpendicular to the plane of the substrate. The second layer and the number of layers forming the substrate are then etched to shape the ferroelectric capacitor device.

Abstract: A method for producing a hard mask and a hard mask for use in a capacitor device comprises the steps of applying a photosensitive sol-gel layer to the capacitor device, applying a pattern to the sol-gel layer to form a patterned layer and applying a thermal decomposition treatment to the patterned layer to convert it to a hard mask layer.

Abstract: A capacitor structure having a capacitor with a top electrode, a bottom electrode, and a capacitor dielectric layer between the top and bottom electrodes is disclosed. The capacitor includes upper and lower portions. The demarcation between the upper and lower portion is located between top and bottom surfaces of the capacitor dielectric layer. A dielectric layer is provided on the sidewalls of the upper portion of the capacitor to prevent shorting between the electrodes that can be caused by a conductive fence formed during processing.

Abstract: A vertical capacitor of an FeRAM device is formed by depositing conductive material and etching it to form electrodes, which are located over openings in an insulating layer so that they are electrically connected to lower levels of the structure. A layer of ferroelectric material is formed on the sides of the electrodes, and etched to a desired, uniform thickness. Conductive material is deposited over the ferroelectric material to form a uniform surface onto which another insulating layer can be deposited. Since this process does not include etching of an insulating layer at a time between the formation of the electrodes and the deposition of the ferroelectric material, no fences of insulating material are formed between them. The geometry can be accurately controlled, to give uniform electric fields and reliable operating parameters.

Abstract: Ferrocapacitors having a vertical structure are formed by a process in which a ferroelectric layer is deposited over an insulator. In a first etching stage, the ferroelectric material is etched to form openings in it, leaving the insulating layer substantially intact. Then a conductive layer is deposited into the openings formed in the ferroelectric layer, forming electrodes on the sides of the openings. Further etching is performed to form gaps in the Al2O3 layer, for making connections to conductive elements beneath it. Thus, by the time the second etching step is performed; there are already electrodes overlying the sides of the ferroelectric material, without insulating fences in between.

Abstract: A device and method for fabricating a device comprises forming a substrate and forming a contact plug through the substrate. A first electrode is formed on the substrate and a dielectric layer is formed on the first electrode. A second electrode is formed on the ferroelectric layer and an interlayer dielectric layer is applied to the second electrode and exposed surfaces of the first electrode and the ferroelectric layer. The interlayer dielectric layer is subjected to a chemical mechanical polishing process to expose a surface of the second electrode and a metal layer is deposited onto the polished interlayer dielectric layer and the exposed surface of the second electrode. The metal layer is then etched to provide an interconnection pattern to the second electrode.