Abstract: To ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to be maintained. IR drop refers to a reduction in the potential difference between the power supply rails and is caused when the switching activity of cells that share a power supply rail is greater than can be provided at a particular time. Before fabrication, placement of the cells is reorganized within bounding box regions. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. The reorganization is IR aware and has minimal impact on timing and IR drop is mitigated because distributing current consumption between the supply rails reduces current spikes and IR drops.

Abstract: Techniques are disclosed herein for designing a circuit. The techniques include receiving a specification for a driver and a plurality of sinks; executing, based on the driver and the plurality of sinks, a machine learning model that predicts at least one of a size, a location, or a delay target of one or more buffers; generating a tree that includes a plurality of nodes representing the driver, the plurality of sinks, and the one or more buffers between the driver and one or more of the sinks; and generating a design of a circuit based on the tree.

Abstract: The present application relates to a novel benzoazepine compound, comprising a pharmaceutically acceptable salt thereof. The present application also provides a pharmaceutical composition comprising the compound and a pharmaceutically acceptable salt thereof. The present application relates to use of the compound and the composition in the prevention or treatment of diseases related to arginine vasopressin V1a receptor, arginine vasopressin V1b receptor, arginine vasopressin V2 receptor, sympathetic nervous system or renin-angiotensin-aldosterone system. The present application also provides a method for preventing and/or treating arginine vasopressin-related diseases.

Abstract: A circuit mask optimizer utilizes a Convolutional Fourier Neural Operator (CFNO) to efficiently learn layout tile dependencies, enabling stitch-less largescale mask optimization with limited intervention of legacy tools. Litho-guided self training via a trained machine learning model provides non-convex optimization, enabling iterative model and dataset refinements at a substantial performance improvement over conventional solutions.

Abstract: A VLSI placement optimization framework receives a cell connectivity representation and cell characteristics and uses self-supervised graph clustering to optimize cell cluster assignments for power, performance, and area (PPA). The framework provides cell clustering constraints as placement guidance to commercial placers. Specifically, graph learning techniques are used to formulate the PPA metrics as machine learning loss functions that can be minimized directly through gradient descent. The framework improves the PPA metrics at the placement stage and the improvements endure to the post-route stage.

Abstract: Self-supervised machine learning is applied to combinational gate sizing based on an input circuit netlist. A transformer neural network architecture is disclosed to select gate sizes along paths of the network between primary inputs/outputs and/or sequential logic elements. The gate size selections may be optimized along dimensions such as path delay, path power consumption, and path circuit area.

Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.

Abstract: As integrated circuit geometries have shrunk, lithography simulation has developed to ensure that the masks used to fabricate the circuits satisfy the chip yield and fabrication turnaround time targets. To manufacture an integrated circuit (chip), an initial layout for the integrated circuit design is processed to compute a wafer image (e.g., resist material “printed” on the wafer using photomasks). Lithography simulation processes the initial layout according to optical physics to compute an estimated wafer image without actually constructing the physical masks or consuming any wafer fabrication resources and may be used to confirm manufacturability of the design layout before it is fabricated. Performing lithography simulation using a dual-band neural network produces accurate results efficiently.

Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.

Abstract: IR drop predictions are obtained using a maximum convolutional neural network. A circuit structure is partitioned into a grid. For cells of the circuit structure in sub-intervals of a clock period, power consumption of the cell is amortized into a set of grid tiles that include portions of the cell, thus forming a set of power maps. The power maps are applied to a neural network to generate IR drop predictions for the circuit structure.

Abstract: To ensure proper operation (e.g., speed and/or function) of standard cells fabricated within an integrated circuit a minimum potential difference between the high and low power supply rails needs to be maintained. IR drop refers to a reduction in the potential difference between the power supply rails and is caused when the switching activity of cells that share a power supply rail is greater than can be provided at a particular time. Before fabrication, placement of the cells is reorganized within bounding box regions. Power density across the power rails within each bounding box is normalized based on spatial and temporal power density characteristics of each cell. The reorganization is IR aware and has minimal impact on timing and IR drop is mitigated because distributing current consumption between the supply rails reduces current spikes and IR drops.

Abstract: To facilitate crosstalk analysis for an IC design, a plurality of input vectors are input into a gate-level simulation. In response, the gate-level simulation determines timing windows for all nets within the IC design, may perform aggressor pruning, and may then determine and output aggressor/victim pairs and associated features for the IC design. This gate-level simulation may be accelerated utilizing one or more graphics processor units (GPUs). Additionally, the aggressor/victim pairs and associated features for the IC design are then input into a trained machine learning environment, which outputs predicted delta delays for each of the aggressor/victim pairs. In this way, crosstalk analysis may be performed more accurately and efficiently.

Abstract: An automatic standard cell layout generator that generates circuit layouts for an industry standard cell library on an advanced technology node leverages reinforcement learning (RL) to generate device placements in the layouts and also to fix design rule violations during routing. A genetic algorithm is utilized to generate routing candidates to which a reinforcement learning model is applied to correct the design rule constraint violations incrementally. A design rule checker provides feedback on the violations to the reinforcement learning model and the model learns how to fix the violations. A layout device placer based upon a simulated annealing method may also be utilized.

Abstract: Today neural networks are used to enable autonomous vehicles and improve the quality of speech recognition, real-time language translation, and online search optimizations. However, operation of the neural networks for these applications consumes energy. Quantization of parameters used by the neural networks reduces the amount of memory needed to store the parameters while also reducing the power consumed during operation of the neural network. Matrix operations performed by the neural networks require many multiplication calculations, so reducing the number of bits that are multiplied reduces the energy that is consumed. Quantizing smaller sets of the parameters using a shared scale factor improves accuracy compared with quantizing larger sets of the parameters. Accuracy of the calculations may be maintained by quantizing and scaling the parameters using fine-grained per-vector scale factors. A vector includes one or more elements within a single dimension of a multi-dimensional matrix.

Abstract: Today neural networks are used to enable autonomous vehicles and improve the quality of speech recognition, real-time language translation, and online search optimizations. However, operation of the neural networks for these applications consumes energy. Quantization of parameters used by the neural networks reduces the amount of memory needed to store the parameters while also reducing the power consumed during operation of the neural network. Matrix operations performed by the neural networks require many multiplication calculations, so reducing the number of bits that are multiplied reduces the energy that is consumed. Quantizing smaller sets of the parameters using a shared scale factor improves accuracy compared with quantizing larger sets of the parameters. Accuracy of the calculations may be maintained by quantizing and scaling the parameters using fine-grained per-vector scale factors. A vector includes one or more elements within a single dimension of a multi-dimensional matrix.

Abstract: The IR drop for a portion of a circuit may include a voltage drop across resistance, and may include a product of current I passing through resistance with a resistance value R. In order to determine IR drop for a circuit in a more accurate and efficient manner, a neural network produces coefficient maps (that each indicate a time-varying distribution of power within an associated portion of the circuit), and these coefficient maps are then used by the neural network to determine an IR drop for each of a plurality of portions of the circuit.

Abstract: A genetic algorithm is utilized to generate routing candidates to which a reinforcement learning model is applied to correct the design rule constraint violations incrementally. A design rule checker provides feedback on the violations to the reinforcement learning model and the model learns how to fix the violations. A layout device placer based upon a simulated annealing method may also be utilized.

Abstract: The disclosure provides a general solution for determining connections between terminals of various types of circuits using machine learning (ML). A ML method that uses reinforcement learning (RL), such as deep RL, to determine and optimize routing of circuit connections using a game process is provided. In one example a method of determining routing connection includes: (1) receiving a circuit design having known terminal groups, (2) establishing terminal positions for the terminal groups in a routing environment, and (3) determining, by the RL agent, routes of nets between the known terminal groups employing a model that is independent of a number of the nets of the circuit. A method of creating a model for routing nets using RL, a method of employing a game for training a RL agent to determine routing connections, and a RL agent for routing connections of a circuit are also disclosed.

Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.

Abstract: A graph neural network for average power estimation of netlists is trained with register toggle rates over a power window from an RTL simulation and gate level netlists as input features. Combinational gate toggle rates are applied as labels. The trained graph neural network is then applied to infer combinational gate toggle rates over a different power window of interest and/or different netlist.