Abstract: To increase the efficiency of electronic design automation, execute partition-aware global routing with track assignment on an electronic data structure including a small block floorplan of a putative integrated circuit design. The small block floorplan is virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks. Based on results of the executing, determine locations, on the inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in the routing, as well as required sizes of the ports. Generate a physical partitioning based on the inter-large-block boundaries; align the ports with the inter-large-block boundaries; and generate a hardware description language design structure encoding the physical partitioning.

Abstract: To increase the efficiency of electronic design automation, execute partition-aware global routing with track assignment on an electronic data structure including a small block floorplan of a putative integrated circuit design. The small block floorplan is virtually partitioned into a proposed large block floorplan with a plurality of inter-large-block boundaries of a plurality of large blocks. Based on results of the executing, determine locations, on the inter-large-block boundaries, of a plurality of required ports corresponding to routes identified in the routing, as well as required sizes of the ports. Generate a physical partitioning based on the inter-large-block boundaries; align the ports with the inter-large-block boundaries; and generate a hardware description language design structure encoding the physical partitioning.

Abstract: Systems and methods to place latches during hierarchical integrated circuit development obtain an initial floor plan indicating a blocked region, two or more regions, and initial locations of components including the latches. A method includes identifying a subset of the latches that belong to a vector as a vector of latches, the subset of the latches being single-bit latches that must be placed in a same one of the two or more regions, and identifying a center of gravity (COG) of the vector of latches, the COG being a mean of geometric points corresponding with the subset of the latches. All of the subset of the latches are placed at the COG to generate an intermediate floor plan based on determining that the COG is not in the blocked region. A final design of the integrated circuit that is obtained based on the intermediate floor plan is provided for fabrication.

Abstract: Embodiments of the invention include method, systems and computer program products for creating a circuit design using a generated tree. The computer-implemented method includes receiving, by one or more processors, a design area for a microelectronic device, wherein the design area includes a plurality of sub-units, each sub-unit from the plurality of sub-units capable of receiving a control signal. The processor determines a location of a source and one or more sinks within the design area. The processor further calculates a center of gravity (COG) based on the location of the one or more sinks. The processor connects the COG to each of the one or more sinks. The processor further connects the COG to the source.

Abstract: A method can include receiving design data of the integrated circuit, the design data indicates a set of sub-units partitioning an area of an integrated circuit, and a clock tree coupling the sub-units, the clock tree including a selected memory element, a predecessor memory element, and successor elements; determining a valid placement region for relocating the selected memory element; generating grid comprising first set of perpendicularly intersecting lines through the selected memory element, predecessor memory element, and successor elements; extending the grid to include second set of perpendicularly intersecting lines through vertices of the valid placement region and through intersections between edges of the valid placement region and the first set of perpendicularly intersecting lines; determining, within the valid placement region, a point in the extended grid having a minimum total rectilinear distance to the predecessor memory element and the successor elements; relocating the memory element to t

Abstract: A method can include receiving design data of the integrated circuit, the design data indicates a set of sub-units partitioning an area of an integrated circuit, and a clock tree coupling the sub-units, the clock tree including a selected memory element, a predecessor memory element, and successor elements; determining a valid placement region for relocating the selected memory element; generating grid comprising first set of perpendicularly intersecting lines through the selected memory element, predecessor memory element, and successor elements; extending the grid to include second set of perpendicularly intersecting lines through vertices of the valid placement region and through intersections between edges of the valid placement region and the first set of perpendicularly intersecting lines; determining, within the valid placement region, a point in the extended grid having a minimum total rectilinear distance to the predecessor memory element and the successor elements; relocating the memory element to t

Abstract: A method includes identifying a design area for a microelectronic device, where the design area includes a plurality of sub-units, each sub-unit from the plurality of sub-units capable of receiving a control signal. The method places a central latch in a center of the design area, where the central latch presents a connection point on a first level of the design area. Responsive to determining a sub-unit of the plurality of sub-units does not include a latch, the method creates a horizontal and vertical axis through the central latch, where the horizontal and vertical axis are bound by a perimeter of the design area. The method places a first set of latches for tiles created by the horizontal axis and the vertical axis on a second level of the design area, where each latch of the first set of latches is placed in a center of a single tile.

Abstract: According to one embodiment of the present invention, a method for reducing congestion in an integrated circuit design is provided. The method may include identifying a net, wherein the net defines a path on one or more of a plurality of conducting layers in an integrated circuit and the net has an associated signal transit time. The method may further include identifying a first subnet of the net in a congested area of the integrated circuit. The method may further include modifying the first subnet, such that the congested area becomes less congested. The method may further include identifying a second subnet of the net in an uncongested area of the integrated circuit. The method may further include modifying the second subnet, such that the signal transit time of the net decreases.

Abstract: According to one embodiment of the present invention, a method for reducing congestion in an integrated circuit design is provided. The method may include identifying a net, wherein the net defines a path on one or more of a plurality of conducting layers in an integrated circuit and the net has an associated signal transit time. The method may further include identifying a first subnet of the net in a congested area of the integrated circuit. The method may further include modifying the first subnet, such that the congested area becomes less congested. The method may further include identifying a second subnet of the net in an uncongested area of the integrated circuit. The method may further include modifying the second subnet, such that the signal transit time of the net decreases.

Abstract: A method and a device for supplying power to one or more microelectronic chips. The method comprises the steps of reading a process characteristic parameter associated with the chip from a non-volatile storage, wherein the process characteristic parameter represents a manufacturing process characteristics of the chip; determining a minimal voltage (VDD_min) based on the parameter; and supplying electric power to the chip (10) with the minimal voltage (VDD_min). The device includes a hardware portion, and a firmware portion wherein the firmware portion includes a unit for determining a minimal voltage (VDD_min) based on a process characteristic parameter of the one or more chips.

Abstract: The present invention pertains to a design method for VLSI-chips. The chips are partitioned into segments in order to enable DRC and LVS. Thus, the memory requirements are kept below the limits of the platform used for the verification and the turnaround time is drastically reduced.

Abstract: An improved wiring structure to minimize coupling between the wiring in one metalization layer of an integrated circuit chip and the wiring in an adjoining metalization layer is described. Wiring in one layer is rotated by an angle a.sub.1 with respect to the direction of the wiring in the adjoining layer. By successively rotating all the conductors of one wiring layer with respect to the wiring of the next layer, the capacitive and inductive coupling between conductors in the various layers is minimized, thereby improving the overall high-frequency performance of the chip.