Patents by Inventor Harald Freudenberger
Harald Freudenberger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11875200Abstract: A message limit value to be used in enqueuing one or more messages on a queue of a device of the computing environment is obtained. The message limit value indicates whether an extended maximum message length is supported by the device. The extended maximum message length is different from a default maximum message length supported by the device. Based on determining that the extended maximum message length is supported and that the obtained message limit value has a defined relationship with a select value, at least one message of an extended length is enqueued on the queue of the device.Type: GrantFiled: September 23, 2021Date of Patent: January 16, 2024Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Louis P. Gomes, Damian Osisek, Harald Freudenberger, Richard John Moore, Volker Urban, Michael D. Hocker, Eric David Rossman, Richard Victor Kisley
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Publication number: 20230089541Abstract: A message limit value to be used in enqueuing one or more messages on a queue of a device of the computing environment is obtained. The message limit value indicates whether an extended maximum message length is supported by the device. The extended maximum message length is different from a default maximum message length supported by the device. Based on determining that the extended maximum message length is supported and that the obtained message limit value has a defined relationship with a select value, at least one message of an extended length is enqueued on the queue of the device.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Inventors: Louis P. Gomes, Damian Osisek, Harald Freudenberger, Richard John Moore, Volker Urban, Michael D. Hocker, Eric David Rossman, Richard Victor Kisley
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Patent number: 11475167Abstract: A security module, such as a cryptographic adapter, is reserved for a secure guest of a computing environment. The reserving includes binding one or more queues of the security module to the secure guest. The one or more queues are then managed based on one or more actions relating to the reservation.Type: GrantFiled: January 29, 2020Date of Patent: October 18, 2022Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Reinhard Theodor Buendgen, Volker Urban, Richard Victor Kisley, Jonathan D. Bradbury, Torsten Hendel, Harald Freudenberger, Benedikt Klotz, Klaus Werner, Markus Selve
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Publication number: 20210232709Abstract: A security module, such as a cryptographic adapter, is reserved for a secure guest of a computing environment. The reserving includes binding one or more queues of the security module to the secure guest. The one or more queues are then managed based on one or more actions relating to the reservation.Type: ApplicationFiled: January 29, 2020Publication date: July 29, 2021Inventors: Reinhard Theodor Buendgen, Volker Urban, Richard Victor Kisley, Jonathan D. Bradbury, Torsten Hendel, Harald Freudenberger, Benedikt Klotz, Klaus Werner, Markus Selve
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Patent number: 10491387Abstract: A method for protecting an encryption key for a block storage device is provided. The includes reading from a superblock of the block storage device a secure key, referring to a clear key only accessible by a hardware security module, and a type indicator indicating that the secure key refers to the clear key which is only accessible by the hardware security module. The method also includes associating the block storage device with the hardware security module and converting the secure key into a protected clear key using the hardware security module, wherein the protected key refers to the clear key accessible by a central processing unit of a related computer system.Type: GrantFiled: November 15, 2016Date of Patent: November 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hendrik S. Brueckner, Reinhard T. Buendgen, Harald Freudenberger
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Patent number: 10169282Abstract: A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as follows: when one of the master devices is using the bus for data communication, then the other master(s) will receive a wait signal until the bus becomes available again. This wait signal allows the master devices to wait as a “hardware response,” rather than requiring the master devices to be equipped with software and/or firmware to control the operation of waiting until the serial bus is available. In some embodiments, the use of the I2C serializer device allows a bus operating under a bus serialization protocol (for example, I2C) to be simultaneously connected to multiple master devices even in the case that one, or more, master device(s) do not include any currently conventional form of multi-master support.Type: GrantFiled: July 7, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventors: Harald Freudenberger, Thomas Hess, Martin Raitza, Philip S. Schulz, Markus Strasser
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Publication number: 20180139046Abstract: A method for protecting an encryption key for a block storage device is provided. The includes reading from a superblock of the block storage device a secure key, referring to a clear key only accessible by a hardware security module, and a type indicator indicating that the secure key refers to the clear key which is only accessible by the hardware security module. The method also includes associating the block storage device with the hardware security module and converting the secure key into a protected clear key using the hardware security module, wherein the protected key refers to the clear key accessible by a central processing unit of a related computer system.Type: ApplicationFiled: November 15, 2016Publication date: May 17, 2018Inventors: HENDRIK S. BRUECKNER, REINHARD T. BUENDGEN, HARALD FREUDENBERGER
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Patent number: 9940282Abstract: A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as follows: when one of the master devices is using the bus for data communication, then the other master(s) will receive a wait signal until the bus becomes available again. This wait signal allows the master devices to wait as a “hardware response,” rather than requiring the master devices to be equipped with software and/or firmware to control the operation of waiting until the serial bus is available. In some embodiments, the use of the I2C serializer device allows a bus operating under a bus serialization protocol (for example, I2C) to be simultaneously connected to multiple master devices even in the case that one, or more, master device(s) do not include any currently conventional form of multi-master support.Type: GrantFiled: March 2, 2017Date of Patent: April 10, 2018Assignee: Inernational Business Machines CorporationInventors: Harald Freudenberger, Thomas Hess, Martin Raitza, Philip S. Schulz, Markus Strasser
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Publication number: 20170315955Abstract: A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as follows: when one of the master devices is using the bus for data communication, then the other master(s) will receive a wait signal until the bus becomes available again. This wait signal allows the master devices to wait as a “hardware response,” rather than requiring the master devices to be equipped with software and/or firmware to control the operation of waiting until the serial bus is available. In some embodiments, the use of the I2C serializer device allows a bus operating under a bus serialization protocol (for example, I2C) to be simultaneously connected to multiple master devices even in the case that one, or more, master device(s) do not include any currently conventional form of multi-master support.Type: ApplicationFiled: July 7, 2017Publication date: November 2, 2017Inventors: Harald Freudenberger, Thomas Hess, Martin Raitza, Philip S. Schulz, Markus Strasser
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Patent number: 9740658Abstract: A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as follows: when one of the master devices is using the bus for data communication, then the other master(s) will receive a wait signal until the bus becomes available again. This wait signal allows the master devices to wait as a “hardware response,” rather than requiring the master devices to be equipped with software and/or firmware to control the operation of waiting until the serial bus is available. In some embodiments, the use of the I2C serializer device allows a bus operating under a bus serialization protocol (for example, I2C) to be simultaneously connected to multiple master devices even in the case that one, or more, master device(s) do not include any currently conventional form of multi-master support.Type: GrantFiled: December 19, 2014Date of Patent: August 22, 2017Assignee: International Business Machines CorporationInventors: Harald Freudenberger, Thomas Hess, Martin Raitza, Philip S. Schulz, Markus Strasser
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Publication number: 20170177531Abstract: A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as follows: when one of the master devices is using the bus for data communication, then the other master(s) will receive a wait signal until the bus becomes available again. This wait signal allows the master devices to wait as a “hardware response,” rather than requiring the master devices to be equipped with software and/or firmware to control the operation of waiting until the serial bus is available. In some embodiments, the use of the I2C serializer device allows a bus operating under a bus serialization protocol (for example, I2C) to be simultaneously connected to multiple master devices even in the case that one, or more, master device(s) do not include any currently conventional form of multi-master support.Type: ApplicationFiled: March 2, 2017Publication date: June 22, 2017Inventors: Harald Freudenberger, Thomas Hess, Martin Raitza, Philip S. Schulz, Markus Strasser
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Patent number: 9665528Abstract: A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as follows: when one of the master devices is using the bus for data communication, then the other master(s) will receive a wait signal until the bus becomes available again. This wait signal allows the master devices to wait as a “hardware response,” rather than requiring the master devices to be equipped with software and/or firmware to control the operation of waiting until the serial bus is available. In some embodiments, the use of the I2C serializer device allows a bus operating under a bus serialization protocol (for example, I2C) to be simultaneously connected to multiple master devices even in the case that one, or more, master device(s) do not include any currently conventional form of multi-master support.Type: GrantFiled: November 20, 2014Date of Patent: May 30, 2017Assignee: International Business Machines CorporationInventors: Harald Freudenberger, Thomas Hess, Martin Raitza, Philip S. Schulz, Markus Strasser
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Publication number: 20160147708Abstract: A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as follows: when one of the master devices is using the bus for data communication, then the other master(s) will receive a wait signal until the bus becomes available again. This wait signal allows the master devices to wait as a “hardware response,” rather than requiring the master devices to be equipped with software and/or firmware to control the operation of waiting until the serial bus is available. In some embodiments, the use of the I2C serializer device allows a bus operating under a bus serialization protocol (for example, I2C) to be simultaneously connected to multiple master devices even in the case that one, or more, master device(s) do not include any currently conventional form of multi-master support.Type: ApplicationFiled: November 20, 2014Publication date: May 26, 2016Inventors: Harald Freudenberger, Thomas Hess, Martin Raitza, Philip S. Schulz, Markus Strasser
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Publication number: 20160147707Abstract: A serial bus is provided with a device (sometimes herein referred to as an I2C serializer device) including circuitry and machine logic that operates as follows: when one of the master devices is using the bus for data communication, then the other master(s) will receive a wait signal until the bus becomes available again. This wait signal allows the master devices to wait as a “hardware response,” rather than requiring the master devices to be equipped with software and/or firmware to control the operation of waiting until the serial bus is available. In some embodiments, the use of the I2C serializer device allows a bus operating under a bus serialization protocol (for example, I2C) to be simultaneously connected to multiple master devices even in the case that one, or more, master device(s) do not include any currently conventional form of multi-master support.Type: ApplicationFiled: December 19, 2014Publication date: May 26, 2016Inventors: Harald Freudenberger, Thomas Hess, Martin Raitza, Philip S. Schulz, Markus Strasser