Abstract: Central processing units have two or more groups of in each case one processor, one memory and one coupler, the processor and memory are connected to exactly one coupler and the couplers are connected to one another. A memory area distributed uniformly over the address space is allocated disjointedly to each group by address interleaving and each coupler itself meets an access to the memory area allocated to its group and meets other accesses via the connection to the coupler concerned. The central processing units are provided with interfaces for building up multiple systems.