Patents by Inventor Haran Thanigasalam
Haran Thanigasalam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220179821Abstract: In one embodiment, a system includes a host system-on-chip (SoC) comprising vision processing circuitry and a camera connected to the host SoC through an Inter-Integrated Circuit (I3C) bus. The camera includes circuitry to generate image data and transmit an interrupt signal to the host SoC over the I3C bus indicating the image data is ready for transfer. The host SoC vision processing circuitry is to transmit a read message to the camera over the I3C bus based on the interrupt signal and receive a set of line payload packets including the image data over the I3C bus based on the read message.Type: ApplicationFiled: February 25, 2022Publication date: June 9, 2022Inventors: Satheesh Chellappan, Haran Thanigasalam
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Patent number: 11249932Abstract: Techniques and mechanisms for communicating packets of image information, the packets each having a respective format that is defined or otherwise indicated by a camera serial interface standard. In an embodiment, circuitry of a first physical layer (PHY) is operated to facilitate such communication via a lane of an interconnect that is coupled between the first PHY and a second PHY. The PHYs further communicate between each other a packet delimiter sequence between two such packets. In another embodiment, the plurality of packets and the packet delimiter sequence are communicated after a transition of one PHY from a relatively low power state, and prior to any subsequent transition of that PHY back to the relatively low power state. The camera serial interface standard specifies or otherwise indicates a protocol whereby a transition to such a low power state is performed between the respective communications of any two successive packets.Type: GrantFiled: May 6, 2020Date of Patent: February 15, 2022Assignee: INTEL CORPORATIONInventors: Haran Thanigasalam, Steven Peterson
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Publication number: 20200356512Abstract: Techniques and mechanisms for communicating packets of image information, the packets each having a respective format that is defined or otherwise indicated by a camera serial interface standard. In an embodiment, circuitry of a first physical layer (PHY) is operated to facilitate such communication via a lane of an interconnect that is coupled between the first PHY and a second PHY. The PHYs further communicate between each other a packet delimiter sequence between two such packets. In another embodiment, the plurality of packets and the packet delimiter sequence are communicated after a transition of one PHY from a relatively low power state, and prior to any subsequent transition of that PHY back to the relatively low power state. The camera serial interface standard specifies or otherwise indicates a protocol whereby a transition to such a low power state is performed between the respective communications of any two successive packets.Type: ApplicationFiled: May 6, 2020Publication date: November 12, 2020Inventors: Haran Thanigasalam, Steven Peterson
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Patent number: 10691629Abstract: Techniques and mechanisms for communicating packets of image information, the packets each having a respective format that is defined or otherwise indicated by a camera serial interface standard. In an embodiment, circuitry of a first physical layer (PHY) is operated to facilitate such communication via a lane of an interconnect that is coupled between the first PHY and a second PHY. The PHYs further communicate between each other a packet delimiter sequence between two such packets. In another embodiment, the plurality of packets and the packet delimiter sequence are communicated after a transition of one PHY from a relatively low power state, and prior to any subsequent transition of that PHY back to the relatively low power state. The camera serial interface standard specifies or otherwise indicates a protocol whereby a transition to such a low power state is performed between the respective communications of any two successive packets.Type: GrantFiled: May 24, 2016Date of Patent: June 23, 2020Assignee: INTEL CORPORATIONInventors: Haran Thanigasalam, Steven Peterson
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Patent number: 10291814Abstract: In one example, a system for transmitting encrypted data includes a processor to select a virtual channel to be encrypted between an application processor and an image sensor during an initialization process. The processor can also transmit a virtual channel command corresponding to the selected virtual channel to the image sensor. The processor can also poll a register in the image sensor to verify the image sensor has stored an encryption key corresponding to the selected virtual channel and detect image data from the image sensor via the virtual channel, the image data encrypted with the encryption key.Type: GrantFiled: October 13, 2017Date of Patent: May 14, 2019Assignee: Intel CorporationInventor: Haran Thanigasalam
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Publication number: 20180285301Abstract: Techniques and mechanisms for communicating packets of image information, the packets each having a respective format that is defined or otherwise indicated by a camera serial interface standard. In an embodiment, circuitry of a first physical layer (PHY) is operated to facilitate such communication via a lane of an interconnect that is coupled between the first PHY and a second PHY. The PHYs further communicate between each other a packet delimiter sequence between two such packets. In another embodiment, the plurality of packets and the packet delimiter sequence are communicated after a transition of one PHY from a relatively low power state, and prior to any subsequent transition of that PHY back to the relatively low power state. The camera serial interface standard specifies or otherwise indicates a protocol whereby a transition to such a low power state is performed between the respective communications of any two successive packets.Type: ApplicationFiled: May 24, 2016Publication date: October 4, 2018Inventors: Haran THANIGASALAM, Steven PETERSON
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Patent number: 10033916Abstract: In one example, a system for modifying transmission of image data includes a processor to detect a camera management command to transmit to an image sensor via a camera serial interface link. The processor can also transmit the camera management command to the image sensor via the camera serial interface link, and receive image data from the image sensor via the camera serial interface link.Type: GrantFiled: August 10, 2016Date of Patent: July 24, 2018Assignee: Intel CorporationInventor: Haran Thanigasalam
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Publication number: 20180109696Abstract: In one example, a system for transmitting encrypted data includes a processor to select a virtual channel to be encrypted between an application processor and an image sensor during an initialization process. The processor can also transmit a virtual channel command corresponding to the selected virtual channel to the image sensor. The processor can also poll a register in the image sensor to verify the image sensor has stored an encryption key corresponding to the selected virtual channel and detect image data from the image sensor via the virtual channel, the image data encrypted with the encryption key.Type: ApplicationFiled: October 13, 2017Publication date: April 19, 2018Applicant: INTEL CORPORATIONInventor: Haran Thanigasalam
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Publication number: 20170359499Abstract: In one example, a system for modifying transmission of image data includes a processor to detect a camera management command to transmit to an image sensor via a camera serial interface link. The processor can also transmit the camera management command to the image sensor via the camera serial interface link, and receive image data from the image sensor via the camera serial interface link.Type: ApplicationFiled: August 10, 2016Publication date: December 14, 2017Applicant: Intel CorporationInventor: Haran Thanigasalam
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Publication number: 20170262395Abstract: Methods, apparati, systems for including interrupt functionality in sensor interconnects field are disclosed in the present disclosure. A System on a Chip (SOC) consistent with the present disclosure includes a host and a unified sensor interconnect. A unified sensor interconnect is to be coupled to the host and at least one device. In one or more implementations, the unified sensor interconnect includes a clock line, data line, ground line, and power source line. Further, the unified sensor interconnect is to enable interrupts from at least one of the host or the at least one device.Type: ApplicationFiled: May 26, 2017Publication date: September 14, 2017Inventors: Haran Thanigasalam, Kenneth Foust, Rajasekaran Andiappan
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Publication number: 20170104733Abstract: Techniques and mechanisms to exchange sensor information between devices. In one embodiment, sensor data and corresponding metadata are stored, respectively, to a first buffer and a second buffer of a first device that is coupled to a host device via a hardware interface of the first device and serial bus. The sensor data and metadata are communicated to the host using a protocol that is compatible with a bidirectional, serial command interface standard. Communication of sensor information between the devices is according to a priority of the second buffer over the first buffer. In another embodiment, the metadata includes a token indicating to the host device a risk of sensor data being overwritten at the first buffer or a risk of the first buffer being starved of sensor data.Type: ApplicationFiled: March 30, 2016Publication date: April 13, 2017Inventor: Haran Thanigasalam
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Publication number: 20140368667Abstract: Apparatus, methods, and systems are herein described for providing a method for calibrating a channel by employing a training sequence during at least one blanking interval. In one embodiment, an apparatus includes a first control logic to send a command to generate a predetermined data pattern during at least one blanking interval. In addition, the apparatus includes a second control logic to determine whether a received data pattern matches the predetermined data pattern.Type: ApplicationFiled: December 29, 2013Publication date: December 18, 2014Inventors: Steven A. Peterson, Haran Thanigasalam, Sriram Balasubrahmanyam
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Patent number: 8867683Abstract: A receiver for receiving a stream of symbols clocked at a first rate, and providing the symbols at a second clock rate uses two buffers. Incoming symbols are written to a first dual clock buffer at the first rate, and read from the first and second buffer, at the second rate. Underflow of the first buffer is signaled to the second buffer, thereby avoiding the need to insert defined clock compensation symbols at the second rate. Symbols received at the second buffer while underflow is signaled may be ignored. Conveniently, the second buffer may also be used to align symbol data across multiple symbol streams using periodic alignment symbols. An exemplary embodiment conforms to the PCI Express standard.Type: GrantFiled: January 27, 2006Date of Patent: October 21, 2014Assignee: ATI Technologies ULCInventor: Haran Thanigasalam
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Publication number: 20140229644Abstract: Methods, apparati, systems for including interrupt functionality in sensor interconnects field are disclosed in the present disclosure. A System on a Chip (SOC) consistent with the present disclosure includes a host and a unified sensor interconnect. A unified sensor interconnect is to be coupled to the host and at least one device. In one or more implementations, the unified sensor interconnect includes a clock line, data line, ground line, and power source line. Further, the unified sensor interconnect is to enable interrupts from at least one of the host or the at least one device.Type: ApplicationFiled: February 11, 2014Publication date: August 14, 2014Inventors: Haran Thanigasalam, Kenneth Foust, Rajasekaran Andiappan
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Publication number: 20070177701Abstract: A receiver for receiving a stream of symbols clocked at a first rate, and providing the symbols at a second clock rate uses two buffers. Incoming symbols are written to a first dual clock buffer at the first rate, and read from the first and second buffer, at the second rate. Underflow of the first buffer is signaled to the second buffer, thereby avoiding the need to insert defined clock compensation symbols at the second rate. Symbols received at the second buffer while underflow is signaled may be ignored. Conveniently, the second buffer may also be used to align symbol data across multiple symbol streams using periodic alignment symbols. An exemplary embodiment conforms to the PCI Express standard.Type: ApplicationFiled: January 27, 2006Publication date: August 2, 2007Inventor: Haran Thanigasalam