Patents by Inventor Haraprasad Nanjundappa

Haraprasad Nanjundappa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit (IC) design analysis and feature extraction
    Patent number: 9754071
    Abstract: Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.
    Type: Grant
    Filed: February 19, 2016
    Date of Patent: September 5, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Haraprasad Nanjundappa, Basanth Jagannathan, Laura S. Chadwick, Dureseti Chidambarrao, Christopher V. Baiocco
  • INTEGRATED CIRCUIT (IC) DESIGN ANALYSIS AND FEATURE EXTRACTION
    Publication number: 20170242952
    Abstract: Various embodiments include approaches for analyzing integrated circuit (IC) designs. In some cases, an approach includes: defining extraction parameters for the design of the IC for each of a set of failure modes; testing the design of the IC for a failure mode in the set of failure modes; identifying a defined extraction parameter from the design of the IC for at least one of the set of failure modes; correlating the identified defined extracted parameter and each of the at least one failure mode for the design of the IC; and creating a normalized parameter equation representing the correlation of the identified defined extraction parameter with the at least one failure mode for the design of the IC in numerical form.
    Type: Application
    Filed: February 19, 2016
    Publication date: August 24, 2017
    Inventors: Haraprasad Nanjundappa, Basanth Jagannathan, Laura S. Chadwick, Dureseti Chidambarrao, Christopher V. Baiocco