Patents by Inventor Harbinder Sikka

Harbinder Sikka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Deep learning based identification of difficult to test nodes
    Patent number: 11574097
    Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: February 7, 2023
    Assignee: NVIDIA CORP.
    Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi
  • DEEP LEARNING BASED IDENTIFICATION OF DIFFICULT TO TEST NODES
    Publication number: 20210295169
    Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
    Type: Application
    Filed: April 15, 2021
    Publication date: September 23, 2021
    Applicant: NVIDIA Corp.
    Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi
  • Deep learning based identification of difficult to test nodes
    Patent number: 11010516
    Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
    Type: Grant
    Filed: August 9, 2019
    Date of Patent: May 18, 2021
    Assignee: NVIDIA Corp.
    Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi
  • Deep learning testability analysis with graph convolutional networks
    Patent number: 10657306
    Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: May 19, 2020
    Assignee: NVIDIA Corp.
    Inventors: Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan
  • DEEP LEARNING BASED IDENTIFICATION OF DIFFICULT TO TEST NODES
    Publication number: 20200151289
    Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
    Type: Application
    Filed: August 9, 2019
    Publication date: May 14, 2020
    Applicant: NVIDIA Corp.
    Inventors: Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, Sandeep Gangundi
  • Deep Learning Testability Analysis with Graph Convolutional Networks
    Publication number: 20200151288
    Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.
    Type: Application
    Filed: July 24, 2019
    Publication date: May 14, 2020
    Applicant: NVIDIA Corp.
    Inventors: Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan