Patents by Inventor Hardik ARORA

Hardik ARORA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Clock multiplexer circuitry with glitch reduction
    Patent number: 11824539
    Abstract: Clock multiplexer circuitry outputs one of a first or second clock signal. First selection circuitry is connected in series with first counter circuitry. The first selection circuitry and the first counter circuitry receive a first clock signal and a first selection signal. A first control signal is generated based on the first clock signal and the first selection signal. Second selection circuitry is connected in series with second counter circuitry. The second selection circuitry and the second counter circuitry receive a second clock signal and a second selection signal. A second control signal is generated based on the second clock signal and the second selection signal. The output circuitry is connected to the first counter circuitry and the second counter circuitry. The output circuitry outputs one of the first clock signal and the second clock signal based on the first control signal and the second control signal.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: November 21, 2023
    Assignee: Synopsys, Inc.
    Inventors: Hardik Arora, Amit Verma, Basannagouda Somanath Reddy
  • CLOCK MULTIPLEXER CIRCUITRY WITH GLITCH REDUCTION
    Publication number: 20230051554
    Abstract: Clock multiplexer circuitry outputs one of a first or second clock signal. First selection circuitry is connected in series with first counter circuitry. The first selection circuitry and the first counter circuitry receive a first clock signal and a first selection signal. A first control signal is generated based on the first clock signal and the first selection signal. Second selection circuitry is connected in series with second counter circuitry. The second selection circuitry and the second counter circuitry receive a second clock signal and a second selection signal. A second control signal is generated based on the second clock signal and the second selection signal. The output circuitry is connected to the first counter circuitry and the second counter circuitry. The output circuitry outputs one of the first clock signal and the second clock signal based on the first control signal and the second control signal.
    Type: Application
    Filed: August 10, 2022
    Publication date: February 16, 2023
    Inventors: Hardik ARORA, Amit VERMA, Basannagouda Somanath REDDY