Abstract: A system and method for reducing peak to average power ratio in a wireless communication system. A wireless communication system includes a radio frequency wireless transmitter that includes signal peak reduction circuitry configured to reduce peak to average power ratio of a signal to be transmitted by reducing amplitude of the signal to be transmitted that is greater than a predetermined amplitude. The signal peak reduction circuitry includes a bit inverter configured to invert a bit of a symbol identified as causing the amplitude of the signal to exceed the predetermined amplitude. The bit inverter is also configured to select the bit to invert such that inversion of the bit reduces the amplitude of the signal, and such that forward error correction in a receiver wirelessly coupled to the transmitter restores the bit to a pre-inversion value.

Abstract: A digital pre-distortion component includes: a first capturing component that captures a first sample set of data; a first generating component that generates a first change matrix associated with a portion of the first sample set of data; a first memory component that stores the first change matrix; a second capturing component that captures a second sample set of data; a second generating component that generates a second change matrix associated with a portion of the second sample set of data; a second memory component that stores the second change matrix; a third capturing component that captures a third sample set of data; a third generating component that generates a third change matrix associated with a portion of the third sample set of data; a comparing component that compares the third change matrix with the first change matrix to obtain a first comparison, and compares the third change matrix with the second change matrix to obtain a second comparison; and an adapting component that adapts the digi

Abstract: A digital pre-distortion component includes: a first capturing component that captures a first sample set of data; a first generating component that generates a first change matrix associated with a portion of the first sample set of data; a first memory component that stores the first change matrix; a second capturing component that captures a second sample set of data; a second generating component that generates a second change matrix associated with a portion of the second sample set of data; a second memory component that stores the second change matrix; a third capturing component that captures a third sample set of data; a third generating component that generates a third change matrix associated with a portion of the third sample set of data; a comparing component that compares the third change matrix with the first change matrix to obtain a first comparison, and compares the third change matrix with the second change matrix to obtain a second comparison; and an adapting component that adapts the digi

Abstract: Embodiments of the present invention disclose a method for facilitating enhanced inter-object and human-object interactivity using networked electronic devices.

Abstract: A method of predistorting an input signal (902) for an amplifier is disclosed (FIG. 9). The method includes predistorting the input signal with a first set of parameters (FDPD) and a second set of parameters (CDPD) at a first time (904). The first set of parameters is updated at a second time (914). The second set of parameters is updated separately from the first set of parameters at a third time (920).

Abstract: A method of predistorting an input signal (902) for an amplifier is disclosed (FIG. 9). The method includes predistorting the input signal with a first set of parameters (FDPD) and a second set of parameters (CDPD) at a first time (904). The first set of parameters is updated at a second time (914). The second set of parameters is updated separately from the first set of parameters at a third time (920).

Abstract: A method of predistorting an input signal (902) for an amplifier is disclosed (FIG. 9). The method includes predistorting the input signal with a first set of parameters (FDPD) and a second set of parameters (CDPD) at a first time (904). The first set of parameters is updated at a second time (914). The second set of parameters is updated separately from the first set of parameters at a third time (920).

Abstract: A system and method for reducing peak to average power ratio in a wireless communication system. A wireless communication system includes a radio frequency wireless transmitter that includes signal peak reduction circuitry configured to reduce peak to average power ratio of a signal to be transmitted by reducing amplitude of the signal to be transmitted that is greater than a predetermined amplitude. The signal peak reduction circuitry includes a bit inverter configured to invert a bit of a symbol identified as causing the amplitude of the signal to exceed the predetermined amplitude. The bit inverter is also configured to select the bit to invert such that inversion of the bit reduces the amplitude of the signal, and such that forward error correction in a receiver wirelessly coupled to the transmitter restores the bit to a pre-inversion value.

Abstract: A method to form a CFR cancellation filter for signals with dynamic power and frequency distribution by estimating the filter at the rate required by the input signal's dynamics. For mixed mode systems (for example CDMA and LTE) the CFR is computed for each stream, and combined to form the final filter.

Abstract: This invention is a method of power amplifier digital pre-distortion which measures a current power level of the power amplifier, stores in a look up table entries consisting of a power level and a corresponding set of digital pre-distortion coefficients, selects a set of digital pre-distortion coefficients corresponding to the measured power level. If the measured current power level is near a power level index, the digital pre-distortion coefficients correspond to the power level index. If the measured current power level is greater than the maximum power level entry, the digital pre-distortion coefficients is of the maximum power level entry. If the measured current power level is less than the minimum power level entry, the digital pre-distortion is of the minimum power level entry. If the measured current power level is not near a power level index, the digital pre-distortion coefficients are an interpolation.

Abstract: A method of predistorting an input signal (902) for an amplifier is disclosed (FIG. 9). The method includes predistorting the input signal with a first set of parameters (FDPD) and a second set of parameters (CDPD) at a first time (904). The first set of parameters is updated at a second time (914). The second set of parameters is updated separately from the first set of parameters at a third time (920).

Abstract: A method to form a CFR cancellation filter for signals with dynamic power and frequency distribution by estimating the filter at the rate required by the input signal's dynamics. For mixed mode systems (for example CDMA and LTE) the CFR is computed for each stream, and combined to form the final filter.

Abstract: Crest factor reduction algorithms described herein may be used to improve power amplifier efficiency during low signal power conditions compared to traditional static threshold techniques. Techniques described herein insure that the signal power level at the output of the crest fact reduction block is held constant relative to the input power level under all signal power level conditions. Two different solutions may be implemented together or separately to achieve the desired conditions. The first technique provides constant ratio between input power and output power. Constant ratio of peak and average output levels keeps the amount of crest factor reduction applied to the signal constant, irrespective of the signal power level. A second technique is to hold signal power level constant in respect to the amount of crest factor reduction applied.

Abstract: An apparatus is provided. In the apparatus, an input to index (I2I) module maps a complex input into a real signal. A real data tap delay line is coupled to the I2I module and includes N delay-elements. A complex data tap delay line is configured to receive the complex input and includes M delay elements. A set of K of non-linear function modules is also provided. Each non-linear function module from the set has at least one real input, at least one complex input, and at least one complex output. A configurable connectivity crossbar multiplexer couples K of the N real tap delay line elements to real inputs of the set non-linear functions and couples K of the M complex tap delay line elements to complex inputs of the set non-linear function modules.

Abstract: A signal processing circuit is configured to calculate a gain ratio to efficiently reduce a peak to average signal ratio for an input signal by identifying signal peaks and determining the signal peak magnitudes. A window function in combination with the gain ratio is applied to a portion of the input stream having a peak signal to create a cancellation pulse to be applied to that peak signal. The cancellation pulse phase is aligned with the signal phase, thereby causing minimal phase distortion in the resultant output signal and accurate peak cancellation. The cancellation pulse can also include a finite impulse response filter portion to efficiently handle wide bandwidth signals. The hardware may be configured to process multiple signal streams in parallel to reduce hardware requirements. An algorithm can determine the effect of multiple corrections to the input stream to avoid overcorrection in the signal processing process.

Abstract: Crest factor reduction algorithms described herein may be used to improve power amplifier efficiency during low signal power conditions compared to traditional static threshold techniques. Techniques described herein insure that the signal power level at the output of the crest fact reduction block is held constant relative to the input power level under all signal power level conditions. Two different solutions may be implemented together or separately to achieve the desired conditions. The first technique provides constant ratio between input power and output power. Constant ratio of peak and average output levels keeps the amount of crest factor reduction applied to the signal constant, irrespective of the signal power level. A second technique is to hold signal power level constant in respect to the amount of crest factor reduction applied.

Abstract: Systems and methods for power amplifier pre-distortion are provided. The systems and methods of power amplifier digital pre-distortion disclosed herein may include a generic pre-distorter architecture which can implement a variety of Volterra cross terms involving single dimension convolutions (first order dynamics). For hardware implementations, this generic pre-distorter is further fine-tuned to provide a choice between different sets of cross terms that can be selected for a given PA for optimal performance. The novel pre-distorter architecture provides flexibility to trade off memory depth for additional Volterra terms and vice versa. A further novelty is the ability to trade off both memory depth and cross terms for a higher sample rate operation, which may enable higher order non-linear pre-distortion, or support for higher signal bandwidths. A poly-phase non-linear filtering mode allows for this flexibility.

Abstract: A signal processing circuit is configured to calculate a gain ratio to efficiently reduce a peak to average signal ratio for an input signal by identifying signal peaks and determining the signal peak magnitudes. A window function in combination with the gain ratio is applied to a portion of the input stream having a peak signal to create a cancellation pulse to be applied to that peak signal. The cancellation pulse phase is aligned with the signal phase, thereby causing minimal phase distortion in the resultant output signal and accurate peak cancellation. The cancellation pulse can also include a finite impulse response filter portion to efficiently handle wide bandwidth signals. The hardware may be configured to process multiple signal streams in parallel to reduce hardware requirements. An algorithm can determine the effect of multiple corrections to the input stream to avoid overcorrection in the signal processing process.