Patents by Inventor Hare K. Verma
Hare K. Verma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10990517Abstract: Examples described herein relate to efficient memory access. An example is a system includes a programmable device, and a memory. The programmable device is coupled to the host and receives the read/write requests and the addresses associated therewith. The programmable device interleaves the read/write requests across multiple communication channels based on a subset of bits within each address. The memory receives the read/write requests from the programmable device. The memory stores contents associated with the addresses for write requests and returns contents associated with the addresses for a read request to the programmable device. The programmable device returns the received contents to the host for processing.Type: GrantFiled: January 28, 2019Date of Patent: April 27, 2021Assignee: XILINX, INC.Inventors: Hare K. Verma, Jiayou Wang, Vincent Mirian
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Patent number: 10963460Abstract: Integrated circuits and methods relating to hardware acceleration include independent, programmable, and parallel processing units (PU) custom-adapted to process a data stream and aggregate the results to respond to a query. In an illustrative example, a data stream from a database may be divided into data blocks and allocated to a corresponding PU. Each data block may be processed by one of the PUs to generate results according to a predetermined instruction set. A concatenate unit may merge and concatenate a result of each data block together to generate an output result for the query. In some embodiments, very large database SQL queries, for example, may be accelerated by hardware PU/concatenate engines implemented in fixed ASIC or reconfigurable FPGA hardware circuitry.Type: GrantFiled: December 6, 2018Date of Patent: March 30, 2021Assignee: XILINX, INC.Inventors: Hare K. Verma, Bing Tian
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Publication number: 20200183937Abstract: Integrated circuits and methods relating to hardware acceleration include independent, programmable, and parallel processing units (PU) custom-adapted to process a data stream and aggregate the results to respond to a query. In an illustrative example, a data stream from a database may be divided into data blocks and allocated to a corresponding PU. Each data block may be processed by one of the PUs to generate results according to a predetermined instruction set. A concatenate unit may merge and concatenate a result of each data block together to generate an output result for the query. In some embodiments, very large database SQL queries, for example, may be accelerated by hardware PU/concatenate engines implemented in fixed ASIC or reconfigurable FPGA hardware circuitry.Type: ApplicationFiled: December 6, 2018Publication date: June 11, 2020Applicant: Xilinx, Inc.Inventors: Hare K. Verma, Bing Tian
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Publication number: 20180373760Abstract: Embodiments herein describe techniques for preparing and executing tasks related to a database query in a database accelerator. In one embodiment, the database accelerator is separate from a host CPU. A database management system (DBMS) can offload tasks corresponding to a database query to the database accelerator. The DBMS can request data from the database relevant to the query and then convert that data into one or more data blocks that are suitable for processing by the database accelerator. In one embodiment, the database accelerator contains individual hardware processing units (PUs) that can process data in parallel or concurrently. In order to process the data concurrently, the data block includes individual PU data blocks that are each intended for a respective PU in the database accelerator.Type: ApplicationFiled: June 23, 2017Publication date: December 27, 2018Applicant: Xilinx, Inc.Inventors: Hare K. Verma, Sonal Santan, Yongjun Wu
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Patent number: 8429214Abstract: A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.Type: GrantFiled: September 17, 2010Date of Patent: April 23, 2013Assignee: Agate Logic, Inc.Inventors: Hare K. Verma, Ravi Sunkavalli, Manoj Gunwani
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Patent number: 8085603Abstract: A memory is disclosed that can be utilized with a field programmable gate array. In some embodiments, the memory can include a memory array comprising a plurality of memory banks, each memory bank including at least one memory block, each of the at least one memory block including an array of memory cells; an address decoder coupled to each of the at least one memory block, the address decoder including a comparator coupled to receive an input address and a block address and provide a compare bit that indicates when a portion of the input address matches the block address, and an OR gate coupled to receive the compare bit and a wildcard bit, the OR gate providing an enable to the memory block when either the compare bit or the wildcard bit is asserted; and a logic unit that receives a mode value and the input address and provides the wildcard bit to each of the address decoders. Data can be simultaneously written into the memory array in patterns in accordance with the mode value.Type: GrantFiled: September 4, 2009Date of Patent: December 27, 2011Assignee: Integrated Device Technology, Inc.Inventors: Manoj Gunwani, Hare K. Verma, Cordell Prater
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Publication number: 20110058431Abstract: A memory is disclosed that can be utilized with a field programmable gate array. In some embodiments, the memory can include a memory array comprising a plurality of memory banks, each memory bank including at least one memory block, each of the at least one memory block including an array of memory cells; an address decoder coupled to each of the at least one memory block, the address decoder including a comparator coupled to receive an input address and a block address and provide a compare bit that indicates when a portion of the input address matches the block address, and an OR gate coupled to receive the compare bit and a wildcard bit, the OR gate providing an enable to the memory block when either the compare bit or the wildcard bit is asserted; and a logic unit that receives a mode value and the input address and provides the wildcard bit to each of the address decoders. Data can be simultaneously written into the memory array in patterns in accordance with the mode value.Type: ApplicationFiled: September 4, 2009Publication date: March 10, 2011Inventors: Manoj Gunwani, Hare K. Verma, Cordell Prater
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Publication number: 20110010406Abstract: A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.Type: ApplicationFiled: September 17, 2010Publication date: January 13, 2011Applicant: AGATE LOGIC, INC.Inventors: Hare K. Verma, Ravi Sunkavalli, Manoj Gunwani
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Patent number: 7836113Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.Type: GrantFiled: October 9, 2006Date of Patent: November 16, 2010Assignee: Agate Logic, Inc.Inventors: Ravi Sunkavalli, Hare K. Verma, Manoj Gunwani, Elliott Delaye
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Patent number: 7814136Abstract: A programmable system is disclosed having multiple configurable floating point units (“FPU”) that are coupled to multiple programmable logic and routing blocks and multiple memories. Each floating point unit has static configuration blocks and dynamic configuration blocks, where the dynamic configuration blocks can be reconfigured to perform a different floating point unit function. A floating point unit includes a pre-normalization for shifting an exponent calculation as well as shifting and aligning a mantissa, and a post-normalization for normalizing and rounding a received input. The post-normalization receives an input Z and realigns the input, normalizes the input and rounds the input Z.Type: GrantFiled: February 1, 2006Date of Patent: October 12, 2010Assignee: Agate Logic, Inc.Inventors: Hare K. Verma, Ravi Sunkavalli, Manoj Gunwani
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Patent number: 7800404Abstract: A programmable logic array for use in a field programmable application specific integrated circuit (ASIC) implementation is provided. The programmable logic array includes programmable logic blocks, and programmable logic interfaces. The programmable logic interfaces couple the programmable logic blocks to external interfaces of the field programmable ASIC, and enable the programmable logic array to be inserted into the field programmable ASIC as a hard macro block.Type: GrantFiled: December 5, 2008Date of Patent: September 21, 2010Assignee: Integrated Device Technology, Inc.Inventors: Hare K Verma, Manoj Gunwani, Conrad Kong, Jai Liu, Nilanjan Chatterjee
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Patent number: 7728623Abstract: A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1.Type: GrantFiled: October 9, 2006Date of Patent: June 1, 2010Assignee: Agate Logic, Inc.Inventors: Hare K. Verma, Ravi Sunkavalli, Sudip Nag, Conrad Kong, Bo Hu, Chandra Mulpuri, Ashok Vittal
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Patent number: 7605605Abstract: A programmable logic structure is disclosed employing input logic routing cell (ILRC) multiplexers and output logic routing cell (OLRC) multiplexers for making local connections between dedicated logic cells. In a simple programmable logic structure, a dedicated logic cell (DLC) is implemented in a programmable logic structure comprising multiple ILRC multiplexers for port A and multiple OLRC multiplexers for port B. In a multi-level programmable logic structure, multiple columns of dedicated logic cells is designed with columns of dedicated local cells adjacent to each other where each DLC column is used to implement a particular logic function. In a first embodiment, local connections can be made between dedicated logic cells, e.g. an OLRC in a first DLC at level L making local point-to-point connections to an ILRC in a second DLC at level L+1.Type: GrantFiled: January 27, 2005Date of Patent: October 20, 2009Assignee: Cswitch CorporationInventors: Hare K. Verma, Ravi Sunkavalli, Sudip Nag, Conrad Kong, Bo Hu, Chandra Mulpuri, Ashok Vittal
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Publication number: 20090160483Abstract: A programmable logic array for use in a field programmable application specific integrated circuit (ASIC) implementation is provided. The programmable logic array includes programmable logic blocks, and programmable logic interfaces. The programmable logic interfaces couple the programmable logic blocks to external interfaces of the field programmable ASIC, and enable the programmable logic array to be inserted into the field programmable ASIC as a hard macro block.Type: ApplicationFiled: December 5, 2008Publication date: June 25, 2009Inventors: Hare K. Verma, Manoj Gunwani, Conrad Kong, Jai Liu, Nilanjan Chatterjee
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Patent number: 7439768Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In some embodiments, the configurable logic function comprises a plurality of look-up tables coupled to a multiplexer with configurable bits that is capable to perform a four 4-input look-up table, one 6-input look-up tables or a 4-to-1 multiplexer. In the first function that operates as the four 4-input look-up table, the dedicated logic cell has four look-up tables for receiving four inputs respectively.Type: GrantFiled: October 9, 2006Date of Patent: October 21, 2008Assignee: CSwitch CorporationInventors: Ravi Sunkavalli, Hare K. Verma, Manoj Gunwani, Elliott Delaye
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Patent number: 7417456Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.Type: GrantFiled: October 9, 2006Date of Patent: August 26, 2008Assignee: CSwitch CorporationInventors: Hare K. Verma, Ravi Sunkavalli, Manoj Gunwani, Chandra Mulpuri
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Patent number: 7417455Abstract: A function generator is described that can be configured as a combinational logic, sequential logic, or routing cell. The function generator couples to a plurality of selector blocks that select a wire from a plurality of inputs. The selected wires are inputs to a function generator. The function generator, when configured as a combinational logic cell, can generate any function of its inputs. The function generator, when configured as a sequential logic cell, behaves as a register, where any of the inputs can be directed to input data, clear, clock enable, or reset signals. The register is configurable to a falling or rising edge flip-flop or a positive or negative level sensitive latch. As a routing element, logic cells selects one of its inputs. The output of the programmable cell can fan out to one or more inputs of another integrated cell.Type: GrantFiled: May 14, 2005Date of Patent: August 26, 2008Assignee: CSwitch CorporationInventors: Hare K. Verma, Ashok Vittal
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Patent number: 7414432Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic function, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.Type: GrantFiled: October 9, 2006Date of Patent: August 19, 2008Assignee: Cswitch CorporationInventors: Hare K. Verma, Ravi Sunkavalli, Manoj Gunwani, Chandra Mulpuri
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Patent number: 7414431Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.Type: GrantFiled: October 9, 2006Date of Patent: August 19, 2008Assignee: Cswitch CorporationInventors: Hare K. Verma, Ravi Sunkavalli, Manoj Gunwani, Elliott Delaye
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Patent number: 7368941Abstract: A dedicated logic cell in a programmable logic structure is described that comprises the following primary components: a configurable logic function or look-up table (LL), a dedicated logic function (DL), a sequential logic function (LS), and a control logic function (LC). In this illustration, the dedicated logic cell comprises two configurable logic functions, two sequential logic functions, a dedicate logic function, and a control logic function. In a first embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-input function, an AND function, an OR function, or an XOR function. In a second embodiment, the dedicated logic cell is constructed with a combination of configurable logic functions that are coupled to a dedicated logic function in order to perform a four 2-to-1 multiplexer function.Type: GrantFiled: February 23, 2005Date of Patent: May 6, 2008Assignee: CSwitch CorporationInventors: Hare K. Verma, Ravi Sunkavalli, Manoj Gunwani, Chandra Mulpuri