Patents by Inventor Hare Krishna Verma
Hare Krishna Verma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11449344Abstract: A processing circuit includes a random access memory (RAM) configured to look up a first next state based on a first address simultaneously with looking up a second next state based on a second address. The first address is formed of a first current state and an input data and the second address is formed of a second current state and the input data. The processing circuit includes a state control circuit that receives the first and second next states, the first current state, and the second current state, and a first-in-first-out (FIFO) memory that stores selected ones of the first and second next states, the first current state, and the second current state. The processing circuit includes a multiplexer configured to selectively pass two states from the FIFO memory or two states from the state control circuit as a third current state and a fourth current state.Type: GrantFiled: April 21, 2020Date of Patent: September 20, 2022Assignee: Xilinx, Inc.Inventors: Sachin Kumawat, Hare Krishna Verma, Vincent Mirian
-
Patent number: 10210914Abstract: A programmable logic array (PLA) is disclosed employing programming logic tile (PLT), System On Chip (SOC) interface bus, Input Output (IO) blocks and Logic Processing Blocks (LPB). SOC processors using SOC interface bus program PLT successively using different configuration memory bank values to realize a logic not limited by the PLT resource counts. Configuration memory blocks comprising of multiple configuration memory banks and configuration programming control logic remove logic processing penalty due to configuration delays. PLT comprises of Programmable Logic Cells (PLC), Programmable Logic Interface (PLY), Embedded Array Blocks (EAB) and configuration memory block. PLA comprises of PLT, IO blocks, SOC interface bus and LPB. PLA accelerates user functionality in as SOC. IO blocks are used to stream data from other SOC components. LPB use PLT to accelerate user specific functionality.Type: GrantFiled: September 22, 2017Date of Patent: February 19, 2019Inventor: Hare Krishna Verma
-
Publication number: 20180012637Abstract: A programmable logic array (PLA) is disclosed employing programming logic tile (PLT), System On Chip (SOC) interface bus, Input Output (IO) blocks and Logic Processing Blocks (LPB). SOC processors using SOC interface bus program PLT successively using different configuration memory bank values to realize a logic not limited by the PLT resource counts. Configuration memory blocks comprising of multiple configuration memory banks and configuration programming control logic remove logic processing penalty due to configuration delays. PLT comprises of Programmable Logic Cells (PLC), Programmable Logic Interface (PLY), Embedded Array Blocks (EAB) and configuration memory block. PLA comprises of PLT, IO blocks, SOC interface bus and LPB. PLA accelerates user functionality in as SOC. IO blocks are used to stream data from other SOC components. LPB use PLT to accelerate user specific functionality.Type: ApplicationFiled: September 22, 2017Publication date: January 11, 2018Inventor: Hare Krishna VERMA
-
Patent number: 9812180Abstract: A programmable logic array (PLA) is disclosed employing programming logic tile (PLT), System On Chip (SOC) interface bus, Input Output (IO) blocks and Logic Processing Blocks (LPB). SOC processors using SOC interface bus program PLT successively using different configuration memory bank values to realize a logic not limited by the PLT resource counts. Configuration memory blocks comprising of multiple configuration memory banks and configuration programming control logic remove logic processing penalty due to configuration delays. PLT comprises of Programmable Logic Cells (PLC), Programmable Logic Interface (PLY), Embedded Array Blocks (EAB) and configuration memory block. PLA comprises of PLT, IO blocks, SOC interface bus and LPB. PLA accelerates user functionality in as SOC. IO blocks are used to stream data from other SOC components. LPB use PLT to accelerate user specific functionality.Type: GrantFiled: January 18, 2016Date of Patent: November 7, 2017Inventor: Hare Krishna Verma
-
Publication number: 20170206939Abstract: A programmable logic array (PLA) is disclosed employing programming logic tile (PLT), System On Chip (SOC) interface bus, Input Output (IO) blocks and Logic Processing Blocks (LPB). SOC processors using SOC interface bus program PLT successively using different configuration memory bank values to realize a logic not limited by the PLT resource counts. Configuration memory blocks comprising of multiple configuration memory banks and configuration programming control logic remove logic processing penalty due to configuration delays. PLT comprises of Programmable Logic Cells (PLC), Programmable Logic Interface (PLY), Embedded Array Blocks (EAB) and configuration memory block. PLA comprises of PLT, IO blocks, SOC interface bus and LPB. PLA accelerates user functionality in as SOC. IO blocks are used to stream data from other SOC components. LPB use PLT to accelerate user specific functionality.Type: ApplicationFiled: January 18, 2016Publication date: July 20, 2017Inventor: Hare Krishna Verma
-
Patent number: 8700837Abstract: A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.Type: GrantFiled: February 6, 2012Date of Patent: April 15, 2014Assignee: Agate Logic, Inc.Inventors: Hare Krishna Verma, Manoj Gunwani, Ravi Sunkavalli
-
Patent number: 8131909Abstract: A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.Type: GrantFiled: September 19, 2007Date of Patent: March 6, 2012Assignee: Agate Logic, Inc.Inventors: Hare Krishna Verma, Manoj Gunwani, Ravi Sunkavalli
-
Patent number: 7970979Abstract: A high performance field programmable gate array is described with one or more signal processing engines coupled to a programmable logic fabric. Each signal processing engine includes a signal processing unit for performing specifying tasks and a bus-based configurable connection box for routing a bus-based input to a bus-based output. The signal processing unit has a floating point unit (FPU)/multiply accumulate (MAC) for computation and register files for storing information. The programmable logic fabric is coupled to the one or more signal processing engines for routing of information between the signal processing engines.Type: GrantFiled: September 19, 2007Date of Patent: June 28, 2011Assignee: Agate Logic, Inc.Inventors: Hare Krishna Verma, Manoj Gunwani, Ravi Sunkavalli
-
Patent number: 7428722Abstract: Logic design apparatus and method provides serial multiplexer chains in a programmable logic fabric, each element in the chain either selects output of block, or passes output from earlier element of the chain. Select line is a decoder structure or output from configurable function generator that is configured at power-on to create correct selection. Using such structure, larger multiplexer, including priority multiplexers, tristate buses or larger look-up tables (LUTs) can be created. These novel structures can implement priority, non-priority or tristate multiplexers.Type: GrantFiled: January 15, 2008Date of Patent: September 23, 2008Assignee: CSwitch CorporationInventors: Ravi Sunkavalli, Hare Krishna Verma, Sudip Nag, Elliott Delaye
-
Publication number: 20080129334Abstract: Logic design apparatus and method provides serial multiplexer chains in a programmable logic fabric, each element in the chain either selects output of block, or passes output from earlier element of the chain. Select line is a decoder structure or output from configurable function generator that is configured at power-on to create correct selection. Using such structure, larger multiplexer, including priority multiplexers, tristate buses or larger look-up tables (LUTs) can be created. These novel structures can implement priority, non-priority or tristate multiplexers.Type: ApplicationFiled: January 15, 2008Publication date: June 5, 2008Applicant: Cswitch CorporationInventors: Ravi Sunkavalli, Hare Krishna Verma, Sudip Nag, Elliott Delaye
-
Patent number: 7358761Abstract: Logic design apparatus and method provides serial multiplexer chains in a programmable logic fabric, each element in the chain either selects output of block, or passes output from earlier element of the chain. Select line is a decoder structure or output from configurable function generator that is configured at power-on to create correct selection. Using such structure, larger multiplexer, including priority multiplexers, tristate buses or larger look-up tables (LUTs) can be created. These novel structures can implement priority, non-priority or tristate multiplexers.Type: GrantFiled: January 21, 2005Date of Patent: April 15, 2008Assignee: Csitch CorporationInventors: Ravi Sunkavalli, Hare Krishna Verma, Sudip Nag, Elliott Delaye
-
Programmable function generator and method operating as combinational, sequential, and routing cells
Patent number: 6980025Abstract: A function generator is described that can be configured as a combinational logic, sequential logic, or routing cell. The function generator couples to a plurality of selector blocks that select a wire from a plurality of inputs. The selected wires are inputs to a function generator. The function generator, when configured as a combinational logic cell, can generate any function of its inputs. The function generator, when configured as a sequential logic cell, behaves as a register, where any of the inputs can be directed to input data, clear, clock enable, or reset signals. The register is configurable to a falling or rising edge flip-flop or a positive or negative level sensitive latch. As a routing element, logic cells selects one of its inputs. The output of the programmable cell can fan out to one or more inputs of another integrated cell.Type: GrantFiled: September 2, 2003Date of Patent: December 27, 2005Assignee: Velogix, Inc.Inventors: Hare Krishna Verma, Ashok Vittal