Abstract: A system 100 for scan testing at least two substantially identical modules 140 and 150 within an integrated circuit is provided. The system 100 includes a first module 140 to receive and process scan input and produce a first scan output. The system 100 includes a second module 150 substantially similar to the first module 140. The second module 150 receives and processes scan input and produces a second scan output. The system 100 also includes a first component 180 to receive the first and second scan outputs and to produce a first output. The first output is used to determine whether the first and second modules 140 and 150 are functioning properly.

Abstract: In general, a built-in self test circuit and method is provided that measures error in any periodic signal and, particularly, a Phase Lock Loop (PLL) output clock signal. The circuit includes a short-pulse generator that generates a short-pulse signal having the same frequency as the phase lock loop output clock signal. Accordingly, a delay chain, including a plurality of delay elements, generates N delayed pulses from the short-pulse signal. A hit-pulse generator receives the N delayed pulses and compares each delayed pulse with the phase lock loop output clock signal 2K times, such that the hit-pulse generator also generates a hit-pulse when both signals are high. It also generates a hit count which represents the number of hit-pulses. After each of the N delayed pulses are compared with the clock signal 2k times, a comparator compares a predetermined set of threshold values corresponding to the cumulative distribution of jitter for a PLL clock signal with the hit count.

Abstract: A system for generating a pruned diagnostic list of potential bridging faults in a circuit includes a pattern generator operable to generate test patterns for testing a circuit and a tester in communication with the pattern generator that is operable to apply the test patterns to the circuit and generate a plurality of resultant vectors. The system also includes a stuck-at fault dictionary including a list of a plurality of nets of the circuit, each net having at least one resultant vector that indicates a potential stuck-at fault at the net. The system further includes a test analysis tool in communication with the pattern generator and the tester, the test analysis tool operable to create an initial logical diagnostic list of tested nets of the circuit associated with the potential stuck-at faults indicated in the stuck-at fault dictionary, the initial logical diagnostic list created in response to the generated plurality of resultant vectors.

Abstract: A method and apparatus to efficiently burn-in electronic circuits (30), where the electronic circuits (30) comprise at least one set of scan chains (18). The method of the invention comprises the steps of: coupling a scan-in channel to the input of each scan chain (18); coupling in parallel each output of each scan chain (18) to form a single compressed scan-out channel for each set of scan chains (18); applying a test data signal to each scan-in channel; and monitoring each signal from each compressed scan-out channel.

Abstract: An improved method for mapping logical function test data of logical integrated circuits to physical representations uses a pruned diagnostic list. The steps include creating a final logical diagnostic list of potential bridging faults in response to testing the circuit for stuck-at faults at a plurality of nets of the circuit, receiving the physical data associated with nets of the circuit, applying adjacency criteria to the physical data, generating a pruned diagnostic list of potential bridging faults in response to applying the adjacency criteria, performing in-line inspection to obtain second localized probable defect data and correlating second localized portable defect data with the pruned diagnostic list.

Abstract: An improved method for mapping logical function test data of logical integrated circuits to physical representations uses a pruned diagnostic list. The steps include creating a final logical diagnostic list of potential bridging faults in response to testing the circuit for stuck-at faults at a plurality of nets of the circuit, receiving the physical data associated with nets of the circuit, applying adjacency criteria to the physical data, generating a pruned diagnostic list of potential bridging faults in response to applying the adjacency criteria, performing in-line inspection to obtain second localized probable defect data and correlating second localized portable defect data with the pruned diagnostic list.

Abstract: The present invention, generally speaking, takes advantage of the foregoing capability to determine and display the X,Y location corresponding to a net name, by translating functional test data of a digital logic chip passed through a simulation model which identifies one or more defective nets of the chip. The defective nets are processed against a database of the foregoing type to obtain X,Y coordinate data for these nets, allowing them to be data logged as physical traces on the chip layout. In accordance with an exemplary embodiment, this mapping is performed by taking the output from a functional tester and translating it from a list of failed scan chains into a list of suspected netlist nodes. The X,Y coordinates of suspected netlist nodes are then identified and stored in a database, providing failure analysis and yield enhancement engineers a starting point for performing failure analysis and for immediately understanding whether “in-line” inspection data can account for a given failure.