Abstract: An eFuse structure is provided, the structure comprising a first fuse link having a first side. The first fuse link having a first indentation on the first side, the first indentation having a non-linear profile. A first dummy structure may be laterally spaced from the first indentation of the first fuse link.

Abstract: Structures for a static random access memory bit cell and methods of forming a structure for a static random access memory bit cell. The structure includes a first field-effect transistor on a first substrate and a second field-effect transistor on a second substrate. The first field-effect transistor includes a first gate, and the second field-effect transistor includes a second gate. The structure further includes a first interconnect structure on the first substrate and a second interconnect structure on the second substrate. The first interconnect structure includes a first metal feature connected to the first gate, and the first metal feature has a first surface. The second interconnect structure includes a second metal feature connected to the second gate, and the second metal feature has a second surface that is connected to the first surface of the first metal feature.

Abstract: Semiconductor memory devices and methods for writing data in memory cells are provided. An exemplary method for writing data in a memory cell includes providing the memory cell with a first pull-up transistor, a first power supply line coupled to the first pull-up transistor, a second pull-up transistor, and a second power supply line coupled to the second pull-up transistor. The method further includes applying a primary voltage from the first power supply line to the first pull-up transistor. The method also includes applying a secondary voltage from the second power supply line to the second pull-up transistor, wherein the secondary voltage is higher than the primary voltage. Further, the method includes performing a write operation to save a selected value in the memory cell.

Abstract: Semiconductor memory devices and methods for writing data in memory cells are provided. An exemplary method for writing data in a memory cell includes providing the memory cell with a first pull-up transistor, a first power supply line coupled to the first pull-up transistor, a second pull-up transistor, and a second power supply line coupled to the second pull-up transistor. The method further includes applying a primary voltage from the first power supply line to the first pull-up transistor. The method also includes applying a secondary voltage from the second power supply line to the second pull-up transistor, wherein the secondary voltage is higher than the primary voltage. Further, the method includes performing a write operation to save a selected value in the memory cell.