Patents by Inventor Hari Cherupalli

Hari Cherupalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10671774
    Abstract: A method for tailoring a bespoke processor includes generating first gate-level activity information of a general purpose processor design for all possible executions of a first target application for any possible inputs to the first target application. The method includes gate cutting and stitching based on the first gate-level activity information to remove unusable gates from the general purpose processor design and reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: June 2, 2020
    Assignees: Regents of the University of Minnesota, The Board of Trustees of the University of Illinois
    Inventors: Hari Cherupalli, Rakesh Kumar, John Sartori
  • Publication number: 20190102563
    Abstract: A method includes receiving a processor design of a processor, receiving an application to be executed by the processor, and receiving a security policy. The method includes simulating the execution of the application on the processor to identify information flow violations generated by the application based on the security policy.
    Type: Application
    Filed: October 2, 2018
    Publication date: April 4, 2019
    Applicants: Regents of the University of Minnesota, University of Illinois at Urbana-Champaign
    Inventors: Hari Cherupalli, Rakesh Kumar, John Sartori, Henry Duwe
  • Publication number: 20180357344
    Abstract: A method for analyzing a processor design includes receiving a design for a processor and receiving an application to be executed by the processor. The method includes simulating the execution of the application on the processor based on the design to identify unexercisable gates of the processor.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 13, 2018
    Applicants: Regents of the University of Minnesota, University of Illinois at Urbana-Champaign
    Inventors: Hari Cherupalli, Rakesh Kumar, John Sartori
  • Publication number: 20180357345
    Abstract: A method for tailoring a bespoke processor includes generating first gate-level activity information of a general purpose processor design for all possible executions of a first target application for any possible inputs to the first target application. The method includes gate cutting and stitching based on the first gate-level activity information to remove unusable gates from the general purpose processor design and reconnect cut connections between the remaining gates of the general purpose processor design to generate a bespoke processor design for the first target application.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 13, 2018
    Applicants: Regents of the University of Minnesota, University of Illinois at Urbana-Champaign
    Inventors: Hari Cherupalli, Rakesh Kumar, John Sartori
  • Publication number: 20180356877
    Abstract: A method includes generating gate-level activity information of a processor design for all possible executions of a target application for any possible inputs to the target application. The method includes performing a constrained timing analysis on the processor design based on the gate-level activity information to determine a minimum operating voltage for executing the target application on the processor.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 13, 2018
    Applicants: Regents of the University of Minnesota, University of Illinois at Urbana-Champaign
    Inventors: Hari Cherupalli, Rakesh Kumar, John Sartori
  • Publication number: 20180121585
    Abstract: A method for analyzing a digital circuit includes performing a hardware simulation for a workload on a digital circuit design to generate an activity file including a plurality of time stamps and a list of gates, nets, pins, or cells that toggled at each corresponding time stamp. The method includes generating a toggled-set for each time stamp in the activity file and analyzing a vertex-induced sub-graph defined by each toggled-set. The method includes determining a characteristic of the digital circuit design over a specified time window based on the analysis of each toggled-set.
    Type: Application
    Filed: November 1, 2017
    Publication date: May 3, 2018
    Applicant: Regents of the University of Minnesota
    Inventors: Hari Cherupalli, John Sartori