Patents by Inventor Hari Daas Angepat

Hari Daas Angepat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11947802
    Abstract: The present disclosure relates to utilizing a buffer management system to efficiently manage and deallocate memory buffers utilized by multiple processing roles on computer hardware devices. For example, the buffer management system utilizes distributed decentralized memory buffer monitoring in connection with augmented buffer pointers to deallocate memory buffers accurately and efficiently. In this manner, the buffer management system provides an efficient approach for multiple processing roles to consume source data stored in a memory buffer and to deallocate the buffer only after all roles have finished using it.
    Type: Grant
    Filed: September 13, 2022
    Date of Patent: April 2, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Yi Yuan, Narayanan Ravichandran, Robert Groza, Jr., Yevgeny Yankilevich, Hari Daas Angepat
  • Publication number: 20240103721
    Abstract: Embodiments of the present disclosure include systems and methods for providing a scalable controller for managing data storages. A system includes a non-volatile memory controller comprising a set of data queues and a set of administrative queues. The system also includes a set of physical storages communicatively coupled to the non-volatile memory controller. A set of logical storages are created from the set of physical storages. A primary non-volatile memory controller is created from the non-volatile memory controller. The primary non-volatile memory controller comprising an administrative queue in the set of administrative queues, a first subset of the set of data queues, and a first subset of the set of logical storages. An extended non-volatile memory controller is created from the non-volatile memory controller. The extended non-volatile memory controller comprising a second subset of the set of data queues and a second subset of the set of logical storages.
    Type: Application
    Filed: September 22, 2022
    Publication date: March 28, 2024
    Inventors: Jacob Kappeler OSHINS, Hari Daas ANGEPAT, Yi YUAN, Vadim MAKHERVAKS
  • Publication number: 20240086072
    Abstract: The present disclosure relates to utilizing a buffer management system to efficiently manage and deallocate memory buffers utilized by multiple processing roles on computer hardware devices. For example, the buffer management system utilizes distributed decentralized memory buffer monitoring in connection with augmented buffer pointers to deallocate memory buffers accurately and efficiently. In this manner, the buffer management system provides an efficient approach for multiple processing roles to consume source data stored in a memory buffer and to deallocate the buffer only after all roles have finished using it.
    Type: Application
    Filed: September 13, 2022
    Publication date: March 14, 2024
    Inventors: Yi YUAN, Narayanan RAVICHANDRAN, Robert GROZA, JR., Yevgeny YANKILEVICH, Hari Daas ANGEPAT
  • Publication number: 20240061689
    Abstract: The present disclosure relates to utilizing a processing engine system to asynchronously cancel outstanding service requests efficiently and flexibly in computing systems. For example, the processing engine system facilitates asynchronous cancellation of requests by utilizing sequence numbers to validate requests at different stages of a request processing flow. In particular, after efficiently performing local cancellation operations, the processing engine system guarantees that resources associated with canceled requests are deallocated and free to process other requests. Indeed, the processing engine system is able to provide this processing resource-free guarantee without contacting or waiting for remote resources to return outstanding processing requests.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Inventors: Yi YUAN, Hari Daas ANGEPAT
  • Patent number: 11386026
    Abstract: Methods, systems, and computer storage media for providing a Shell PCIe Bridge (SPB) and shared-link-interface services that support a shared common PCIe physical link between SPB clients in a PCIe system. In operation, shared-link-interface operations include accessing, at a Shell PCIe Bridge (SPB), an outbound transaction for a PCIe endpoint vendor IP or an inbound transaction for an SPB client. The SPB supports a shared common PCIe physical link based on a shared-link-interface comprising vendor-agnostic downstream custom interface and a vendor-specific upstream PCIe endpoint interface. The shared-link-interface operations further include processing the outbound transaction or the inbound transaction based on shared-link-interface services. In this way, processing transaction comprises executing shared-link-interface operations that provide protection enhancements associated with sharing a physical PCIe link.
    Type: Grant
    Filed: February 9, 2021
    Date of Patent: July 12, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Narayanan Ravichandran, Aaron Michael Landy, Robert Groza, Jr., Hari Daas Angepat