Patents by Inventor Hari Kannan

Hari Kannan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240143439
    Abstract: A method for adjustable error correction in a storage cluster is provided. The method includes determining health of a non-volatile memory of a non-volatile solid-state storage unit of each of a plurality of storage nodes in a storage cluster on a basis of per flash package, per flash die, per flash plane, per flash block, or per flash page. The determining is performed by the storage cluster. The plurality of storage nodes is housed within a chassis that couples the storage nodes as the storage cluster. The method includes adjusting erasure coding across the plurality of storage nodes based on the health of the non-volatile memory and distributing user data throughout the plurality of storage nodes through the erasure coding. The user data is accessible via the erasure coding from a remainder of the plurality of storage nodes if any of the plurality of storage nodes are unreachable.
    Type: Application
    Filed: November 22, 2022
    Publication date: May 2, 2024
    Inventors: John D. Davis, John Hayes, Zhangxi Tan, Hari Kannan, Nenad Miladinovic
  • Patent number: 11971828
    Abstract: A method for hardware assisted data lookup in a storage unit is provided. The method includes formatting data in at least one of a plurality of data formats for storage in the storage unit. The method includes configuring a logic unit with one or more parameters associated with the plurality of data formats and identifying incoming data with the one or more parameters as an instruction for execution.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: April 30, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Brian T. Gold, John Hayes, Hari Kannan
  • Patent number: 11966841
    Abstract: An apparatus for artificial intelligence acceleration is provided. The apparatus includes a storage and compute system having a distributed, redundant key value store for metadata. The storage and compute system having distributed compute resources configurable to access, through a plurality of authorities, data in the solid-state memory, run inference with a deep learning model, generate vectors for the data and store the vectors in the key value store.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: April 23, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Fabio Margaglia, Emily Potyraj, Hari Kannan, Cary A. Sandvig
  • Patent number: 11960466
    Abstract: This application relates to automatic processes that service data requests for information related to an item during varying temporal periods. For example, a computing device receives first attributes for an item, and generates a first surrogate key and a first super surrogate key based on the first attributes. Further, the computing device generates a first entry within a first table that includes the first surrogate key and the first super surrogate key. The computing device joins the first table to a second table based on natural keys. The computing device also receives second attributes for the item, and generates a second surrogate key for the item based on the second attributes. Further, the computing device generates a second entry within the first table that includes the second surrogate key and the first super surrogate key. The computing device also adjusts the first super surrogate key within the first entry.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: April 16, 2024
    Assignee: Walmart Apollo, LLC
    Inventors: Sivakumar Subramanian, Deekkan Kannan, Hari Sai Gangadhar V, Joyan Sil
  • Patent number: 11955187
    Abstract: A method for processing blocks of flash memory to decrease raw bit errors from the flash memory is provided. The method includes identifying one or more blocks of the flash memory for a refresh operation and writing information regarding the identified blocks, to a data structure. The method includes issuing background reads to the identified blocks, according to the data structure, as the refresh operation. The method may be embodied on a computer readable medium. In some embodiments the background reads may be based on a time based refresh responsive to an increase in raw bit error count in the flash memory over time.
    Type: Grant
    Filed: February 28, 2022
    Date of Patent: April 9, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Hari Kannan, Robert Lee, Yuhong Mao
  • Patent number: 11886334
    Abstract: A storage system has NVRAM (non-volatile random-access memory), solid-state storage memory, and a processor to perform a method. The method includes allocating virtual units of NVRAM with mapping of the virtual units to physical memory. The method includes writing data having various sizes into allocated first virtual units of memory and into allocated second virtual units of memory. The first virtual units of memory each include a first contiguous physical addressed amount of NVRAM having a first size. The second virtual units of memory each include an amount of NVRAM having a second size. The method includes relocating at least some of the data such that a portion of the allocated second virtual units of memory become available for the allocating.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: January 30, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Hari Kannan, Ying Gao, Boris Feigin
  • Patent number: 11869583
    Abstract: A method for page writes for triple or higher level cell flash memory is provided. The method includes receiving data in a storage system, from a client that is agnostic of page write requirements for triple or higher level cell flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages. The method includes accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple or higher level cell flash memory in the storage system. The method includes writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or the higher level cell, flash memory in the storage system as an atomic write.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: January 9, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Hari Kannan, Peter E. Kirkpatrick
  • Patent number: 11868309
    Abstract: A priority queue including an order of local data relocation operations to be performed by a plurality of solid-state storage devices is maintained. An indication of a new local data relocation operation is received from a solid-state storage device of the plurality of solid-state storage devices for data stored at the solid-state storage device, the indication including information associated with the data. The new local data relocation operation is inserted into a position in the order of the priority queue based on the information associated with the data.
    Type: Grant
    Filed: December 6, 2021
    Date of Patent: January 9, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Sankara Vaideeswaran, Hari Kannan, Gordon James Coleman
  • Patent number: 11861188
    Abstract: A storage system, blades, removable modules, and method of configuring a storage system are described. The storage system has blades with computing resources and storage resources. At least one of the blades has, or has added, one or more removable modules.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: January 2, 2024
    Assignee: PURE STORAGE, INC.
    Inventors: Hari Kannan, Yuhong Mao, Mark Heuchert
  • Publication number: 20230418496
    Abstract: One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.
    Type: Application
    Filed: September 1, 2023
    Publication date: December 28, 2023
    Inventors: HARI KANNAN, GORDON JAMES COLEMAN, YIJIE ZHAO, PETER E. KIRKPATRICK, ROBERT LEE, YUHONG MAO, BORIS FEIGIN
  • Publication number: 20230393742
    Abstract: A read request with a high priority indication is received. A determination as to whether an in progress flash programming operation would delay processing the read request for a threshold amount of time is made. In response to determining that the in progress flash programming operation delays processing the read request for the threshold amount of time, the in progress flash programming operation is interrupted.
    Type: Application
    Filed: June 5, 2023
    Publication date: December 7, 2023
    Inventors: RONALD KARR, HARI KANNAN, ROBERT LEE, PETER E. KIRKPATRICK
  • Publication number: 20230333781
    Abstract: A redundant array of independent drives (RAID) stripe is formed across a set of storage controllers of a plurality of storage controllers, wherein the RAID stripe comprises two or more of a plurality of modular storage devices of at least one of the set of storage controllers. The RAID stripe is written across the set of storage controllers.
    Type: Application
    Filed: June 23, 2023
    Publication date: October 19, 2023
    Inventors: HARI KANNAN, ROBERT LEE, YUHONG MAO, RONALD KARR, BORIS FEIGIN
  • Patent number: 11789626
    Abstract: One or more performance parameters associated with data stored at a storage device of a plurality of storage devices are received by a storage controller. A first number of blocks of the storage device to a high resiliency portion and a second number of blocks of the storage device to a low resiliency portion of the storage device are allocated based on the one or more performance parameters.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: October 17, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Hari Kannan, Gordon James Coleman, Yijie Zhao, Peter E. Kirkpatrick, Robert Lee, Yuhong Mao, Boris Feigin
  • Publication number: 20230281177
    Abstract: A storage system is provided. The storage system include a primary storage node that includes a primary processing device. The primary storage node is communicatively coupled to a secondary storage node. The secondary storage node includes a secondary processing device and a set of non-volatile memory modules. The primary processing device is to identify one or more storage operations to be performed on the set of non-volatile memory modules of the secondary storage node and transmit one or more instructions to the secondary storage node to perform the one or more storage operations, the one or more storage operations performed by the secondary processing device.
    Type: Application
    Filed: March 1, 2023
    Publication date: September 7, 2023
    Inventors: HARI KANNAN, YING GAO, BORIS FEIGIN, ROBERT LEE
  • Patent number: 11740802
    Abstract: A method for erasure detection in a storage cluster is provided. The method includes establishing a connection, via a network, of a storage unit to one of a plurality of storage nodes of a storage cluster and determining, for at least one page of a storage memory of the storage unit, that the at least one page is erased. The storage unit is one of a plurality of storage units configured to store user data in memory of the storage units in accordance with direction from the plurality of storage nodes. The method includes communicating from the storage unit to the one of the plurality of storage nodes that the at least one page is erased.
    Type: Grant
    Filed: July 29, 2021
    Date of Patent: August 29, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: John Martin Hayes, Hari Kannan, Nenad Miladinovic
  • Publication number: 20230267040
    Abstract: In some embodiments, a method for die-level monitoring is provided. The method includes distributing user data throughout a plurality of storage nodes through erasure coding, wherein the plurality of storage nodes are housed within a chassis that couples the storage nodes. Each of the storage nodes has a non-volatile solid-state storage with non-volatile memory and the user data is accessible via the erasure coding from a remainder of the storage nodes in event of two of the storage nodes being unreachable. The method includes producing diagnostic information that diagnoses the non-volatile memory on a basis of per package, per die, per plane, per block, or per page, the producing performed by each of the plurality of storage nodes. The method includes writing the diagnostic information to a memory in the storage cluster.
    Type: Application
    Filed: May 1, 2023
    Publication date: August 24, 2023
    Inventors: JOHN D. DAVIS, JOHN HAYES, HARI KANNAN, NENAD MILADINOVIC, ZHANGXI TAN
  • Publication number: 20230251797
    Abstract: A first set of physical units of a storage device of a storage system is selected for performance of low latency access operations, wherein other access operations are performed by remaining physical units of the storage device. A determination as to whether a triggering event has occurred that causes a selection of a new set of physical units of the storage device for the performance of low latency access operations is made. A second set of physical units of the storage device is selected for the performance of low latency access operations upon determining that the triggering event has occurred.
    Type: Application
    Filed: March 27, 2023
    Publication date: August 10, 2023
    Inventors: HARI KANNAN, BORIS FEIGIN, YING GAO, JOHN COLGROVE
  • Publication number: 20230251944
    Abstract: A plurality of storage nodes within a single chassis is provided. The plurality of storage nodes is configured to communicate together as a storage cluster. The plurality of storage nodes has a non-volatile solid-state storage for user data storage. The plurality of storage nodes is configured to distribute the user data and metadata associated with the user data throughout the plurality of storage nodes, with erasure coding of the user data. The plurality of storage nodes is configured to recover from failure of two of the plurality of storage nodes by applying the erasure coding to the user data from a remainder of the plurality of storage nodes. The plurality of storage nodes is configured to detect an error and engage in an error recovery via one of a processor of one of the plurality of storage nodes, a processor of the non-volatile solid state storage, or the flash memory.
    Type: Application
    Filed: April 3, 2023
    Publication date: August 10, 2023
    Inventors: JOHN D. DAVIS, JOHN HAYES, HARI KANNAN, NENAD MILADINOVIC, ZHANGXI TAN
  • Patent number: 11714572
    Abstract: A redundant array of independent drives (RAID) stripe is formed across a set of storage controllers of a plurality of storage controllers, wherein the RAID stripe comprises two or more of a plurality of modular storage devices of at least one of the set of storage controllers. The RAID stripe is written across the set of storage controllers.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: August 1, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Hari Kannan, Robert Lee, Yuhong Mao, Ronald Karr, Boris Feigin
  • Publication number: 20230229552
    Abstract: An indication is received from a storage device that an attempt to read a portion of data from a block of the storage device has failed. A command is transmitted to the storage device to perform a scan on data stored at the block comprising the portion of data to acquire failure information associated with a plurality of subsets of the data stored at the block. The failure information associated with the plurality of subsets of the data stored at the block is received from the storage device.
    Type: Application
    Filed: February 24, 2023
    Publication date: July 20, 2023
    Inventors: DAMIAN YURZOLA, VIDYABHUSHAN MOHAN, GORDON JAMES COLEMAN, MELISSA KIMBLE, HARI KANNAN