Patents by Inventor Hari Mony
Hari Mony has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10394987Abstract: Aspects of the present invention include methods, systems and computer program products. The method includes a processor providing a netlist indicative of connectivity and functional states of components of an integrated circuit design; iteratively searching through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations; adaptively adjusting the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations; and adaptively adjusting an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations.Type: GrantFiled: March 21, 2017Date of Patent: August 27, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jason R. Baumgartner, Raj K. Gajavelly, Hari Mony, Pradeep K. Nalla
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Patent number: 10210296Abstract: Aspects of the present invention include methods, systems and computer program products. The method includes a processor providing a netlist indicative of connectivity and functional states of components of an integrated circuit design; iteratively searching through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations; adaptively adjusting the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations; and adaptively adjusting an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations.Type: GrantFiled: October 24, 2017Date of Patent: February 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jason R. Baumgartner, Raj K. Gajavelly, Hari Mony, Pradeep K. Nalla
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Publication number: 20180276317Abstract: Aspects of the present invention include methods, systems and computer program products. The method includes a processor providing a netlist indicative of connectivity and functional states of components of an integrated circuit design; iteratively searching through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations; adaptively adjusting the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations; and adaptively adjusting an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations.Type: ApplicationFiled: March 21, 2017Publication date: September 27, 2018Inventors: Jason R. Baumgartner, Raj K. Gajavelly, Hari Mony, Pradeep K. Nalla
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Publication number: 20180276318Abstract: Aspects of the present invention include methods, systems and computer program products. The method includes a processor providing a netlist indicative of connectivity and functional states of components of an integrated circuit design; iteratively searching through the netlist at a selected depth to locate errors within the netlist by a plurality of trials, each of the plurality of trials having a plurality of iterations; adaptively adjusting the selected depth depending on any errors within the netlist being located, the selected depth increasing over time from an initial value as between the plurality of iterations; and adaptively adjusting an amount of coverage of the netlist depending on any errors within the netlist being located, the amount of coverage of the netlist decreasing over time from an initial amount as between the plurality of iterations.Type: ApplicationFiled: October 24, 2017Publication date: September 27, 2018Inventors: Jason R. Baumgartner, Raj K. Gajavelly, Hari Mony, Pradeep K. Nalla
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Patent number: 9483595Abstract: Liveness verification of a logic design is performed using various shadow abstraction refinement techniques. An initial subset of state elements are included in the shadow abstraction, and verification is performed (liveness-to-safety conversion) using this initial subset. If a liveness counterexample is detected, the shadow abstraction is refined by designating a second subset of the state elements different from the initial subset for inclusion in a refined abstraction. The initial subset can be designated by choosing all registers in a combinational fan-in of a liveness property of the design. High-performance algorithms for abstract liveness-to-safety conversion can be based upon simulation and counterexample refinement, bounded model checking and counterexample refinement, bounded model checking and proof-based refinement, proofs obtained during bounded model checking of a precise liveness checking problem, a hybrid of counterexample-based refinement and proof analysis, and proofs obtained.Type: GrantFiled: June 3, 2015Date of Patent: November 1, 2016Assignee: International Business Machines CorporationInventors: Jason R. Baumgartner, Raj K. Gajavelly, Robert L. Kanzelman, Hari Mony, Pradeep K. Nalla
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Patent number: 9471734Abstract: Liveness verification of a logic design is performed using various shadow abstraction refinement techniques. An initial subset of state elements are included in the shadow abstraction, and verification is performed (liveness-to-safety conversion) using this initial subset. If a liveness counterexample is detected, the shadow abstraction is refined by designating a second subset of the state elements different from the initial subset for inclusion in a refined abstraction. The initial subset can be designated by choosing all registers in a combinational fan-in of a liveness property of the design. High-performance algorithms for abstract liveness-to-safety conversion can be based upon simulation and counterexample refinement, bounded model checking and counterexample refinement, bounded model checking and proof-based refinement, proofs obtained during bounded model checking of a precise liveness checking problem, a hybrid of counterexample-based refinement and proof analysis, and proofs obtained.Type: GrantFiled: January 19, 2015Date of Patent: October 18, 2016Assignee: International Business Machines CorporationInventors: Jason R. Baumgartner, Raj K. Gajavelly, Robert L. Kanzelman, Hari Mony, Pradeep K. Nalla
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Publication number: 20160210389Abstract: Liveness verification of a logic design is performed using various shadow abstraction refinement techniques. An initial subset of state elements are included in the shadow abstraction, and verification is performed (liveness-to-safety conversion) using this initial subset. If a liveness counterexample is detected, the shadow abstraction is refined by designating a second subset of the state elements different from the initial subset for inclusion in a refined abstraction. The initial subset can be designated by choosing all registers in a combinational fan-in of a liveness property of the design. High-performance algorithms for abstract liveness-to-safety conversion can be based upon simulation and counterexample refinement, bounded model checking and counterexample refinement, bounded model checking and proof-based refinement, proofs obtained during bounded model checking of a precise liveness checking problem, a hybrid of counterexample-based refinement and proof analysis, and proofs obtained.Type: ApplicationFiled: June 3, 2015Publication date: July 21, 2016Inventors: Jason R. Baumgartner, Raj K. Gajavelly, Robert L. Kanzelman, Hari Mony, Pradeep K. Nalla
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Publication number: 20160210388Abstract: Liveness verification of a logic design is performed using various shadow abstraction refinement techniques. An initial subset of state elements are included in the shadow abstraction, and verification is performed (liveness-to-safety conversion) using this initial subset. If a liveness counterexample is detected, the shadow abstraction is refined by designating a second subset of the state elements different from the initial subset for inclusion in a refined abstraction. The initial subset can be designated by choosing all registers in a combinational fan-in of a liveness property of the design. High-performance algorithms for abstract liveness-to-safety conversion can be based upon simulation and counterexample refinement, bounded model checking and counterexample refinement, bounded model checking and proof-based refinement, proofs obtained during bounded model checking of a precise liveness checking problem, a hybrid of counterexample-based refinement and proof analysis, and proofs obtained.Type: ApplicationFiled: January 19, 2015Publication date: July 21, 2016Inventors: Jason R. Baumgartner, Raj K. Gajavelly, Robert L. Kanzelman, Hari Mony, Pradeep K. Nalla
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Patent number: 9280626Abstract: A mechanism is provided for efficiently determining Boolean satisfiability (SAT) using lazy constraints. A determination is made as to whether a SAT problem is satisfied without constraints in a list of constraints. Responsive to the SAT problem being satisfied without constraints, a set of variable assignments that are determined in satisfying the SAT problem without constraints are fixed. For each constraint in the list of constraints, a determination is made as to whether the SAT problem with the constraint results in the set of variable assignments remaining constant. Responsive to the SAT problem with the constraint resulting in the set of variable assignments remaining constant, the constraint is added to a list of non-affecting constraints and a satisfied result is returned.Type: GrantFiled: April 27, 2012Date of Patent: March 8, 2016Assignee: International Business Machines CorporationInventors: Jason R. Baumgartner, Michael L. Case, Robert L. Kanzelman, Hari Mony
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Patent number: 8997030Abstract: An approach is provided in which a model verification system partitions one of a design specification's circuit design properties into multiple unsolved cases. The model verification system then performs property checking on one of the unsolved cases against a corresponding circuit design model, which results in a property checked solved case and a subset of unsolved cases. In turn, the model verification system performs sequential equivalence checking on one or more of the subset of unsolved cases by checking their sequential equivalence against the property checked solved case. As a result, the model verification system stores the cases as sequentially equivalent solved cases and verifies of a portion of the design specification against a portion of the circuit design model.Type: GrantFiled: October 28, 2013Date of Patent: March 31, 2015Assignee: International Business Machines CorporationInventors: Krishnan K. Kailas, Hari Mony
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Publication number: 20150074628Abstract: An approach is provided in which a model verification system partitions one of a design specification's circuit design properties into multiple unsolved cases. The model verification system then performs property checking on one of the unsolved cases against a corresponding circuit design model, which results in a property checked solved case and a subset of unsolved cases. In turn, the model verification system performs sequential equivalence checking on one or more of the subset of unsolved cases by checking their sequential equivalence against the property checked solved case. As a result, the model verification system stores the cases as sequentially equivalent solved cases and verifies of a portion of the design specification against a portion of the circuit design model.Type: ApplicationFiled: September 11, 2013Publication date: March 12, 2015Applicant: International Business Machines CorporationInventors: Krishnan K. Kailas, Hari Mony
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Publication number: 20150074624Abstract: An approach is provided in which a model verification system partitions one of a design specification's circuit design properties into multiple unsolved cases. The model verification system then performs property checking on one of the unsolved cases against a corresponding circuit design model, which results in a property checked solved case and a subset of unsolved cases. In turn, the model verification system performs sequential equivalence checking on one or more of the subset of unsolved cases by checking their sequential equivalence against the property checked solved case. As a result, the model verification system stores the cases as sequentially equivalent solved cases and verifies of a portion of the design specification against a portion of the circuit design model.Type: ApplicationFiled: October 28, 2013Publication date: March 12, 2015Applicant: International Business Machines CorporationInventors: Krishnan K. Kailas, Hari Mony
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Patent number: 8978001Abstract: An approach is provided in which a model verification system partitions one of a design specification's circuit design properties into multiple unsolved cases. The model verification system then performs property checking on one of the unsolved cases against a corresponding circuit design model, which results in a property checked solved case and a subset of unsolved cases. In turn, the model verification system performs sequential equivalence checking on one or more of the subset of unsolved cases by checking their sequential equivalence against the property checked solved case. As a result, the model verification system stores the cases as sequentially equivalent solved cases and verifies of a portion of the design specification against a portion of the circuit design model.Type: GrantFiled: September 11, 2013Date of Patent: March 10, 2015Assignee: International Business Machines CorporationInventors: Krishnan K. Kailas, Hari Mony
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Patent number: 8850372Abstract: A computer-implemented method of invariant-guided abstraction includes a processor of a computing device generating one or more invariants corresponding to a design under verification by executing a proof algorithm with an input comprising at least a portion of the design and a specified resource limit. The method further includes deterministically assigning priority information to the one or more invariants generated and to components of the design referenced by said invariants. Finally, the method includes performing invariant-guided localization abstraction on the design model to generate an abstracted design model utilizing the assigned priority information as a localization hint that results in abstractions that are at least one of (a) smaller abstractions and (b) easier to verify abstractions.Type: GrantFiled: October 19, 2012Date of Patent: September 30, 2014Assignee: International Business Machines CorporationInventors: Jason Raymond Baumgartner, Alexander Ivrii, Arie Matsliah, Hari Mony
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Publication number: 20140115548Abstract: A computer-implemented method of invariant-guided abstraction includes a processor of a computing device generating one or more invariants corresponding to a design under verification by executing a proof algorithm with an input comprising at least a portion of the design and a specified resource limit. The method further includes deterministically assigning priority information to the one or more invariants generated and to components of the design referenced by said invariants. Finally, the method includes performing invariant-guided localization abstraction on the design model to generate an abstracted design model utilizing the assigned priority information as a localization hint that results in abstractions that are at least one of (a) smaller abstractions and (b) easier to verify abstractions.Type: ApplicationFiled: October 19, 2012Publication date: April 24, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: JASON RAYMOND BAUMGARTNER, ALEXANDER IVRII, ARIE MATSLIAH, HARI MONY
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Patent number: 8589837Abstract: A computer-implemented method simplifies a netlist, verifies the simplified netlist using induction, and remaps resulting inductive counterexamples via inductive trace lifting within a multi-algorithm verification framework. The method includes: a processor deriving a first unreachable state information that can be utilized to simplify the netlist; performing a simplification of the netlist utilizing the first unreachable state information; determining whether the first unreachable state information can be inductively proved on an original version of the netlist; and in response to the first unreachable state information not being inductively provable on the original netlist: projecting the first unreachable state information to a minimal subset; and adding the projected unreachable state information as an invariant to further constrain a child induction process.Type: GrantFiled: April 25, 2012Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Jason R. Baumgartner, Michael L. Case, Robert L. Kanzelman, Hari Mony
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Patent number: 8589327Abstract: A mechanism is provided for efficiently determining Boolean satisfiability (SAT) using lazy constraints. A determination is made as to whether a SAT problem is satisfied without constraints in a list of constraints. Responsive to the SAT problem being satisfied without constraints, a set of variable assignments that are determined in satisfying the SAT problem without constraints are fixed. For each constraint in the list of constraints, a determination is made as to whether the SAT problem with the constraint results in the set of variable assignments remaining constant. Responsive to the SAT problem with the constraint resulting in the set of variable assignments remaining constant, the constraint is added to a list of non-affecting constraints and a satisfied result is returned.Type: GrantFiled: April 22, 2011Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Jason R. Baumgartner, Michael L. Case, Robert L. Kanzelman, Hari Mony
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Publication number: 20130305197Abstract: A computer-implemented method includes a processor identifying, within the netlist, at least one strongly connected components (SCCs) that has a reconvergent fanin input with at least two input paths from the reconvergent fanin input having a different propagation delay to the SCC. The method then computes an additive diameter for the netlist comprising at least one SCC, where the additive diameter includes a fanin additive diameter determined based on a propagation delay difference of the at least two input paths to a SCC and a number of complex feed-forward components within at least one input path. In response to the reconvergent fanin input to the SCC providing a binate function, the method computes a multiplicative diameter for the SCC utilizing a least common multiple (LCM) derived from one or more propagation delay differences across each reconvergent fanin input leading to the SCC.Type: ApplicationFiled: May 9, 2012Publication date: November 14, 2013Applicant: IBM CORPORATIONInventors: Jason R. Baumgartner, Robert L. Kanzelman, Hari Mony
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Patent number: 8578311Abstract: A computer-implemented method includes a processor identifying, within the netlist, at least one strongly connected components (SCCs) that has a reconvergent fanin input with at least two input paths from the reconvergent fanin input having a different propagation delay to the SCC. The method then computes an additive diameter for the netlist comprising at least one SCC, where the additive diameter includes a fanin additive diameter determined based on a propagation delay difference of the at least two input paths to a SCC and a number of complex feed-forward components within at least one input path. In response to the reconvergent fanin input to the SCC providing a binate function, the method computes a multiplicative diameter for the SCC utilizing a least common multiple (LCM) derived from one or more propagation delay differences across each reconvergent fanin input leading to the SCC.Type: GrantFiled: May 9, 2012Date of Patent: November 5, 2013Assignee: International Business Machines CorporationInventors: Jason R. Baumgartner, Michael L. Case, Robert L. Kanzelman, Hari Mony
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Publication number: 20130290918Abstract: A computer-implemented method simplifies a netlist, verifies the simplified netlist using induction, and remaps resulting inductive counterexamples via inductive trace lifting within a multi-algorithm verification framework. The method includes: a processor deriving a first unreachable state information that can be utilized to simplify the netlist; performing a simplification of the netlist utilizing the first unreachable state information; determining whether the first unreachable state information can be inductively proved on an original version of the netlist; and in response to the first unreachable state information not being inductively provable on the original netlist: projecting the first unreachable state information to a minimal subset; and adding the projected unreachable state information as an invariant to further constrain a child induction process.Type: ApplicationFiled: April 25, 2012Publication date: October 31, 2013Applicant: IBM CorporationInventors: Jason R. Baumgartner, Robert L. Kanzelman, Hari Mony