Abstract: During electron beam imaging of a semiconductor wafer, the electron beam is adjusted to a first electron dose/nm2/time value below a damage threshold for an image frame grab of a site on the semiconductor wafer. Then the electron beam is adjusted to a second electron dose/nm2/time value different from the first electron dose/nm2/time value for a second image frame grab of the site. The second electron dose/nm2/time value can be above the damage threshold.

Abstract: A defect in an image of a semiconductor wafer can be classified as an initial defect type based on the pixels in the image. Critical dimension uniformity parameters associated with the defect type can be retrieved from an electronic data storage unit. A level of defectivity of the defect can be quantified based on the critical dimension uniformity parameters. Defects also can be classified based on critical dimension attributes, topography attributes, or contrast attributes to determine a final defect type.

Abstract: A method of forming a directed self-assembled (DSA) layer on a substrate by: providing a substrate; applying a layer comprising a self-assembly material on the substrate; and annealing of the self-assembly material of the layer to form a directed self-assembled layer by providing a controlled temperature and gas environment around the substrate. The controlled gas environment comprises molecules comprising an oxygen element with a partial pressure between 10-2000 Pa.

Abstract: Methods and systems for quantifying and correcting for non-uniformities in images used for metrology operations are disclosed. A metrology area image of a wafer and a design clip may be used. The metrology area image may be a scanning electron microscope image. The design clip may be the design clip of the wafer or a synthesized design clip. Tool distortions, including electron beam distortions, can be quantified and corrected. The design clip can be applied to the metrology area image to obtain a synthesized image such that one or more process change variations are suppressed and one or more tool distortions are enhanced.

Abstract: A defect in an image of a semiconductor wafer can be classified as an initial defect type based on the pixels in the image. Critical dimension uniformity parameters associated with the defect type can be retrieved from an electronic data storage unit. A level of defectivity of the defect can be quantified based on the critical dimension uniformity parameters. Defects also can be classified based on critical dimension attributes, topography attributes, or contrast attributes to determine a final defect type.

Abstract: Processes to generate regions of interest for critical dimension uniformity measurement are disclosed. A pattern description based on historical data or a coordinate may be used as input. A pattern of interest can be determined, and then a region of interest can be determined. Instructions can be sent to a wafer inspection tool to image the region of interest on the semiconductor wafer.

Abstract: A sample analysis system includes a scanning electron microscope, an optical and/or eBeam inspection system, and an optical metrology system. The system further includes at least one controller. The controller is configured to receive a first plurality of selected regions of interest of the sample; generate a first critical dimension uniformity map based on a first inspection performed by the scanning electron microscope at the first selected regions of interest; determine a second plurality of selected regions of interest based on the first critical dimension uniformity map; generate a second critical dimension uniformity map based on a second inspection performed by the optical and/or eBeam inspection system at the second selected regions of interest; and determine one or more process tool control parameters based on inspection results and on overlay measurements performed on the sample by the optical metrology system.

Abstract: Methods and systems for quantifying and correcting for non-uniformities in images used for metrology operations are disclosed. A metrology area image of a wafer and a design clip may be used. The metrology area image may be a scanning electron microscope image. The design clip may be the design clip of the wafer or a synthesized design clip. Tool distortions, including electron beam distortions, can be quantified and corrected. The design clip can be applied to the metrology area image to obtain a synthesized image such that one or more process change variations are suppressed and one or more tool distortions are enhanced.

Abstract: A method of forming a directed self-assembled (DSA) layer on a substrate by: providing a substrate; applying a layer comprising a self-assembly material on the substrate; and annealing of the self-assembly material of the layer to form a directed self-assembled layer by providing a controlled temperature and gas environment around the substrate. The controlled gas environment comprises molecules comprising an oxygen element with a partial pressure between 10-2000 Pa.

Abstract: The present disclosure relates to directed self-assembly using trench assisted chemoepitaxy. An example embodiment includes a method of forming a pre-patterned structure for directing a self-assembly of a self-assembling material that includes a first and a second component having different chemical natures. The method includes providing an assembly includes a substrate, a layer of pinning material overlying the substrate, and a resist pattern overlaying the layer of pinning material. The method also includes modifying a chemical nature of an exposed part of a top surface of the layer of pinning material. The method further includes removing the resist pattern. In addition, the method includes attaching a neutral layer to the layer of pinning material.

Abstract: The present disclosure relates to directed self-assembly using trench assisted chemoepitaxy. An example embodiment includes a method of forming a pre-patterned structure for directing a self-assembly of a self-assembling material that includes a first and a second component having different chemical natures. The method includes providing an assembly includes a substrate, a layer of pinning material overlying the substrate, and a resist pattern overlaying the layer of pinning material. The method also includes modifying a chemical nature of an exposed part of a top surface of the layer of pinning material. The method further includes removing the resist pattern. In addition, the method includes attaching a neutral layer to the layer of pinning material.

Abstract: The present disclosure is related to a method for forming a catalyst nanoparticle on a metal surface, the nanoparticle being suitable for growing a single nanostructure, in particular a carbon nanotube, the method comprising at least the steps of: providing a substrate, having a metal layer on at least a portion of the substrate surface, depositing a sacrificial layer at least on the metal layer, producing a small hole in the sacrificial layer, thereby exposing the metal layer, providing a single catalyst nanoparticle into the hole, removing the sacrificial layer. The disclosure is further related to growing a carbon nanotube from the catalyst nanoparticle.

Abstract: The present disclosure is related to a method for forming a catalyst nanoparticle on a metal surface, the nanoparticle being suitable for growing a single nanostructure, in particular a carbon nanotube, the method comprising at least the steps of: providing a substrate, having a metal layer on at least a portion of the substrate surface, depositing a sacrificial layer at least on the metal layer, producing a small hole in the sacrificial layer, thereby exposing the metal layer, providing a single catalyst nanoparticle into the hole, removing the sacrificial layer. The disclosure is further related to growing a carbon nanotube from the catalyst nanoparticle.