Abstract: A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where a simulation trace that causes the property to fail covers the cover directive. Thereafter, the property is evaluated, and dependent on the evaluation, the simulation trace is dumped and stored for subsequent exercising of the cover directive.

Abstract: A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where wherein a simulation trace that causes the property to fail covers the cover directive. Thereafter, the property is evaluated, and dependent on the evaluation, the simulation trace is dumped and stored for subsequent exercising of the cover directive.

Abstract: A method and system for generating test vectors for testing scan-based sequential circuits that contain non-scan cells using combinational ATPG techniques. The present invention includes the computer implemented step of receiving a netlist description of an integrated circuit device that comprises scan cells and non-scannable cells. Under certain conditions, some non-scan cells may exhibit sequential transparency behavior. The present invention identifies such conditions and characterizes each non-scan cell as sequentially transparent or non-transparent. Based on such characterization, the present invention transforms non-scan cells exhibiting sequential transparency behavior with transparent logic models during combinational ATPG (Automatic Test Pattern Generation) analysis. Because non-scan cells of exhibiting sequential transparency behavior are not replaced with “force-to-X” models, the fault coverage of the test patterns thus generated is significantly improved.