Abstract: In order to reduce errors in the transfer of time from one clock domain to another clock domain, a first free running counter is incremented using a first clock signal. A free running second counter is incremented using a second clock signal, the second clock signal being asynchronous to the first clock signal. The first counter is sampled at a selected time based on a predetermined phase relationship between the first clock signal and the second clock signal to generate a sampled first counter value. The second counter is corrected based on the sampled first counter value.

Abstract: Clocking systems are disclosed. A clocking system can include first and second clock domains. Each clock domain can include circuitry with a counter. The clocking system can measure timing errors between these two domains by measuring a phase difference and determining a residual error. Based on the measured timing error, the clocking system can synchronize the time in the first and second clock domains by using at least one of the counters.

Abstract: Clocking systems are disclosed. A clocking system can include first and second clock domains. Each clock domain can include circuitry with a counter. The clocking system can measure timing errors between these two domains by measuring a phase difference and determining a residual error. Based on the measured timing error, the clocking system can synchronize the time in the first and second clock domains by using at least one of the counters.

Abstract: Clocking systems are disclosed. A clocking system can include first and second clock domains. Each clock domain can include circuitry with a counter. The clocking system can measure timing errors between these two domains by measuring a phase difference and determining a residual error. Based on the measured timing error, the clocking system can synchronize the time in the first and second clock domains by using at least one of the counters.

Abstract: In order to reduce errors in the transfer of time from one clock domain to another clock domain, a first free running counter is incremented using a first clock signal. A free running second counter is incremented using a second clock signal, the second clock signal being asynchronous to the first clock signal. The first counter is sampled at a selected time based on a predetermined phase relationship between the first clock signal and the second clock signal to generate a sampled first counter value. The second counter is corrected based on the sampled first counter value.

Abstract: Clocking systems are disclosed. A clocking system can include first and second clock domains. Each clock domain can include circuitry with a counter. The clocking system can measure timing errors between these two domains by measuring a phase difference and determining a residual error. Based on the measured timing error, the clocking system can synchronize the time in the first and second clock domains by using at least one of the counters.

Abstract: Clocking systems are disclosed. A clocking system can include first and second clock domains. Each clock domain can include circuitry with a counter. The clocking system can measure timing errors between these two domains by measuring a phase difference and determining a residual error. Based on the measured timing error, the clocking system can synchronize the time in the first and second clock domains by using at least one of the counters.

Abstract: Clocking systems are disclosed. A clocking system can include first and second clock domains. Each clock domain can include circuitry with a counter. The clocking system can measure timing errors between these two domains by measuring a phase difference and determining a residual error. Based on the measured timing error, the clocking system can synchronize the time in the first and second clock domains by using at least one of the counters.

Abstract: In order to reduce errors in the transfer of time from one clock domain to another clock domain, a first free running counter is incremented using a first clock signal. A free running second counter is incremented using a second clock signal, the second clock signal being asynchronous to the first clock signal. The first counter is sampled at a selected time based on a predetermined phase relationship between the first clock signal and the second clock signal to generate a sampled first counter value. The second counter is corrected based on the sampled first counter value.

Abstract: In order to reduce errors in the transfer of time from one clock domain to another clock domain, a first free running counter is incremented using a first clock signal. A free running second counter is incremented using a second clock signal, the second clock signal being asynchronous to the first clock signal. The first counter is sampled at a selected time based on a predetermined phase relationship between the first clock signal and the second clock signal to generate a sampled first counter value. The second counter is corrected based on the sampled first counter value.

Abstract: A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.

Abstract: A clock product includes a first phase-locked loop circuit including a first frequency divider. The first phase-locked loop circuit is configured to generate a first clock signal tracking a first reference clock signal and a second reference clock signal. The first phase-locked loop circuit is controlled by a first divide value and a first divide value adjustment based on the first reference clock signal. The clock product includes a circuit including a second frequency divider. The circuit is configured to generate a second clock signal based on the first clock signal, a second divide value, and a second divide value adjustment. The second clock signal tracks the second reference clock signal. The second divide value adjustment is based on the first divide value adjustment and opposes the first divide value adjustment.

Abstract: A method for generating a clock signal includes selecting a primary reference clock signal or a secondary reference clock signal as a reference clock signal for a phase-locked loop configured to generate an output clock signal. The method includes generating an indication of whether a failure of the reference clock signal has occurred by monitoring the secondary reference clock signal and a plurality of additional clock signals using the reference clock signal. The failure is determined based on whether a gross failure of the reference clock signal has occurred and if the gross failure has not occurred, further based on whether a quality failure of the reference clock signal has occurred.

Abstract: In order to reduce errors in the transfer of time from one clock domain to another clock domain, a first free running counter is incremented using a first clock signal. A free running second counter is incremented using a second clock signal, the second clock signal being asynchronous to the first clock signal. The first counter is sampled at a selected time based on a predetermined phase relationship between the first clock signal and the second clock signal to generate a sampled first counter value. The second counter is corrected based on the sampled first counter value.

Abstract: A method includes generating first frequency metrics for a first received network clock signal using a local reference clock signal. The method includes, in response to the first received network clock signal being available and satisfying a quality metric, generating a network delay estimate using a first error estimate based on the first received network clock signal, and updating stored frequency metrics for the first received network clock signal with the first frequency metrics. The method includes generating an output clock signal based on received packets and the network delay estimate. The first frequency metrics for the first received network clock signal may include a current average frequency count, a prior average frequency count, a standard deviation of prior average frequency counts and a multiplicative constant corresponding to a number of samples used to determine the current average frequency count, prior average frequency count, and standard deviation.

Abstract: A method for operating a clock product includes generating a quality determination for a reference clock signal based on frequency metrics for a plurality of independent clock signals. The frequency metrics are generated using the reference clock signal. The method includes generating an output clock signal by locking to an active clock signal selected from the plurality of independent clock signals in response to the quality determination satisfying a predetermined quality metric. For each input clock signal of the plurality of independent clock signals, the frequency metrics include a current average frequency count, a prior average frequency count, a standard deviation of prior average frequency counts, and a multiplicative constant corresponding to a number of samples used to determine the current average frequency count, prior average frequency count, and standard deviation.