Patents by Inventor Hariharan Lakshminarayanan Thantry

Hariharan Lakshminarayanan Thantry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240267260
    Abstract: Generally disclosed herein is an approach for maintaining packet ordering in a flow in the presence of table updates. The approach may provide a solution that mitigates correctness issues when there is an addition of instructions to hardware such as a circuit switch or a router while maintaining high packet processing rates. The approach may also include adding a software interface for a table update that is capable of receiving a certain ordering constraint that may influence table operation commands.
    Type: Application
    Filed: February 1, 2023
    Publication date: August 8, 2024
    Inventors: Hariharan Lakshminarayanan Thantry, Rajeev Nair
  • Patent number: 11960772
    Abstract: An apparatus includes an output bus configured to store data, a match table, one or more storage devices, and logic. The match table is configured to store a plurality of entries, each entry including a key value, wherein the match table specifies a matching entry in response to being queried by the query data. The one or more storage devices are configured to store operation information for each of the plurality of entries stored in the match table. The operation information specifies one or more instructions associated with each respective entry in the plurality of entries stored in the match table. The logic is configured to receive one or more operands from the output bus, identify one or more instructions from the one or more storage devices, and generate, based on the one or more instructions and the one or more operands, processed data.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: April 16, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Hariharan Lakshminarayanan Thantry, Srihari Raju Vegesna, Sureshkumar Nedunchezhian, Stimit Kishor Oak
  • Publication number: 20230185490
    Abstract: An apparatus includes an output bus configured to store data, a match table, one or more storage devices, and logic. The match table is configured to store a plurality of entries, each entry including a key value, wherein the match table specifies a matching entry in response to being queried by the query data. The one or more storage devices are configured to store operation information for each of the plurality of entries stored in the match table. The operation information specifies one or more instructions associated with each respective entry in the plurality of entries stored in the match table. The logic is configured to receive one or more operands from the output bus, identify one or more instructions from the one or more storage devices, and generate, based on the one or more instructions and the one or more operands, processed data.
    Type: Application
    Filed: February 10, 2023
    Publication date: June 15, 2023
    Inventors: Hariharan Lakshminarayanan Thantry, Srihari Raju Vegesna, Sureshkumar Nedunchezhian, Stimit Kishor Oak
  • Patent number: 11579802
    Abstract: An apparatus includes an output bus configured to store data, a match table, one or more storage devices, and logic. The match table is configured to store a plurality of entries, each entry including a key value, wherein the match table specifies a matching entry in response to being queried by the query data. The one or more storage devices are configured to store operation information for each of the plurality of entries stored in the match table. The operation information specifies one or more instructions associated with each respective entry in the plurality of entries stored in the match table. The logic is configured to receive one or more operands from the output bus, identify one or more instructions from the one or more storage devices, and generate, based on the one or more instructions and the one or more operands, processed data.
    Type: Grant
    Filed: October 2, 2020
    Date of Patent: February 14, 2023
    Assignee: FUNGIBLE, INC.
    Inventors: Hariharan Lakshminarayanan Thantry, Srihari Raju Vegesna, Sureshkumar Nedunchezhian, Stimit Kishor Oak
  • Patent number: 11218574
    Abstract: This disclosure describes techniques that include representing, traversing, and processing directed graphs using one or more content-addressable memory devices. In one example, this disclosure describes a method that includes presenting query data to one or more ternary content-addressable memory (TCAM) devices, wherein the query data includes state data and key data; receiving, from the TCAM devices, information about a matching address identified by the TCAM devices; accessing, based on the information about the matching address, information in one or more storage devices; performing, based on the information in the one or more storage devices, at least one operation on data included within the one or more storage devices to generate processed data; outputting the processed data; determining, based on the information in the one or more storage devices, new state data and a new key value; and presenting new query data to the TCAM devices.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: January 4, 2022
    Assignee: Fungible, Inc.
    Inventors: Hariharan Lakshminarayanan Thantry, Rohit Sunkam Ramanujam, John David Huber, Deepak Goel, Vikas Minglani
  • Patent number: 11038993
    Abstract: Aspects of this disclosure describes techniques for parsing network packets, processing network packets, and modifying network packets before forwarding the modified network packets over a network. The present disclosure describes a system that, in some examples, parses network packets, generates data describing or specifying attributes of the network packet, identifies operations to be performed when processing a network packet, performs the identified operations, generates data describing or specifying how to modify and/or forward the network packet, modifies the network packet, and outputs the modified packet to another device or system, such as a switch.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: June 15, 2021
    Assignee: FUNGIBLE, INC.
    Inventors: Deepak Goel, Jean-Marc Frailong, Srihari Raju Vegesna, Stimit Kishor Oak, Rohit Sunkam Ramanujam, John David Huber, Hariharan Lakshminarayanan Thantry, Vikas Minglani, Saurin Patel, Sureshkumar Nedunchezhian
  • Publication number: 20210103408
    Abstract: An apparatus includes an output bus configured to store data, a match table, one or more storage devices, and logic. The match table is configured to store a plurality of entries, each entry including a key value, wherein the match table specifies a matching entry in response to being queried by the query data. The one or more storage devices are configured to store operation information for each of the plurality of entries stored in the match table. The operation information specifies one or more instructions associated with each respective entry in the plurality of entries stored in the match table. The logic is configured to receive one or more operands from the output bus, identify one or more instructions from the one or more storage devices, and generate, based on the one or more instructions and the one or more operands, processed data.
    Type: Application
    Filed: October 2, 2020
    Publication date: April 8, 2021
    Inventors: Hariharan Lakshminarayanan Thantry, Srihari Raju Vegesna, Sureshkumar Nedunchezhian, Stimit Kishor Oak
  • Patent number: 10958770
    Abstract: This disclosure describes techniques that include storing, during parsing of a data unit or a network packet, information (i.e., “summary information”) that identifies how the network packet has been process and/or other aspects of the parsing process. In one example, this disclosure describes a method that includes parsing a packet header from a data unit, wherein parsing the packet header includes storing in result vector storage each of a plurality of data items derived from the packet header, the result vector storage having a result vector format defining fields within the result vector storage for storing each of the plurality of data items; storing in template storage, for each of the plurality of data items, summary information about the plurality of data items stored in the result vector storage; and processing, by the packet-processing integrated circuit and based on the summary information and the plurality of data items, the network packet.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: March 23, 2021
    Assignee: Fungible, Inc.
    Inventors: Hariharan Lakshminarayanan Thantry, Srihari Raju Vegesna, Stimit Kishor Oak, Vikas Minglani, Rohit Sunkam Ramanujam, John David Huber, Deepak Goel
  • Publication number: 20200120191
    Abstract: This disclosure describes techniques that include storing, during parsing of a data unit or a network packet, information (i.e., “summary information”) that identifies how the network packet has been process and/or other aspects of the parsing process. In one example, this disclosure describes a method that includes parsing a packet header from a data unit, wherein parsing the packet header includes storing in result vector storage each of a plurality of data items derived from the packet header, the result vector storage having a result vector format defining fields within the result vector storage for storing each of the plurality of data items; storing in template storage, for each of the plurality of data items, summary information about the plurality of data items stored in the result vector storage; and processing, by the packet-processing integrated circuit and based on the summary information and the plurality of data items, the network packet.
    Type: Application
    Filed: October 15, 2018
    Publication date: April 16, 2020
    Inventors: Hariharan Lakshminarayanan Thantry, Srihari Raju Vegesna, Stimit Kishor Oak, Vikas Minglani, Rohit Sunkam Ramanujam, John David Huber, Deepak Goel
  • Publication number: 20190379770
    Abstract: This disclosure describes techniques that include representing, traversing, and processing directed graphs using one or more content-addressable memory devices. In one example, this disclosure describes a method that includes presenting query data to one or more ternary content-addressable memory (TCAM) devices, wherein the query data includes state data and key data; receiving, from the TCAM devices, information about a matching address identified by the TCAM devices; accessing, based on the information about the matching address, information in one or more storage devices; performing, based on the information in the one or more storage devices, at least one operation on data included within the one or more storage devices to generate processed data; outputting the processed data; determining, based on the information in the one or more storage devices, new state data and a new key value; and presenting new query data to the TCAM devices.
    Type: Application
    Filed: June 7, 2019
    Publication date: December 12, 2019
    Inventors: Hariharan Lakshminarayanan Thantry, Rohit Sunkam Ramanujam, John David Huber, Deepak Goel, Vikas Minglani
  • Publication number: 20190289102
    Abstract: Aspects of this disclosure describes techniques for parsing network packets, processing network packets, and modifying network packets before forwarding the modified network packets over a network. The present disclosure describes a system that, in some examples, parses network packets, generates data describing or specifying attributes of the network packet, identifies operations to be performed when processing a network packet, performs the identified operations, generates data describing or specifying how to modify and/or forward the network packet, modifies the network packet, and outputs the modified packet to another device or system, such as a switch.
    Type: Application
    Filed: March 13, 2019
    Publication date: September 19, 2019
    Inventors: Deepak Goel, Jean-Marc Frailong, Srihari Raju Vegesna, Stimit Kishor Oak, Rohit Sunkam Ramanujam, John David Huber, Hariharan Lakshminarayanan Thantry, Vikas Minglani, Saurin Patel, Sureshkumar Nedunchezhian