Patents by Inventor Hariharan Lakshminarayanan Thantry
Hariharan Lakshminarayanan Thantry has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240267260Abstract: Generally disclosed herein is an approach for maintaining packet ordering in a flow in the presence of table updates. The approach may provide a solution that mitigates correctness issues when there is an addition of instructions to hardware such as a circuit switch or a router while maintaining high packet processing rates. The approach may also include adding a software interface for a table update that is capable of receiving a certain ordering constraint that may influence table operation commands.Type: ApplicationFiled: February 1, 2023Publication date: August 8, 2024Inventors: Hariharan Lakshminarayanan Thantry, Rajeev Nair
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Patent number: 11960772Abstract: An apparatus includes an output bus configured to store data, a match table, one or more storage devices, and logic. The match table is configured to store a plurality of entries, each entry including a key value, wherein the match table specifies a matching entry in response to being queried by the query data. The one or more storage devices are configured to store operation information for each of the plurality of entries stored in the match table. The operation information specifies one or more instructions associated with each respective entry in the plurality of entries stored in the match table. The logic is configured to receive one or more operands from the output bus, identify one or more instructions from the one or more storage devices, and generate, based on the one or more instructions and the one or more operands, processed data.Type: GrantFiled: February 10, 2023Date of Patent: April 16, 2024Assignee: Microsoft Technology Licensing, LLCInventors: Hariharan Lakshminarayanan Thantry, Srihari Raju Vegesna, Sureshkumar Nedunchezhian, Stimit Kishor Oak
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Publication number: 20230185490Abstract: An apparatus includes an output bus configured to store data, a match table, one or more storage devices, and logic. The match table is configured to store a plurality of entries, each entry including a key value, wherein the match table specifies a matching entry in response to being queried by the query data. The one or more storage devices are configured to store operation information for each of the plurality of entries stored in the match table. The operation information specifies one or more instructions associated with each respective entry in the plurality of entries stored in the match table. The logic is configured to receive one or more operands from the output bus, identify one or more instructions from the one or more storage devices, and generate, based on the one or more instructions and the one or more operands, processed data.Type: ApplicationFiled: February 10, 2023Publication date: June 15, 2023Inventors: Hariharan Lakshminarayanan Thantry, Srihari Raju Vegesna, Sureshkumar Nedunchezhian, Stimit Kishor Oak
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Patent number: 11579802Abstract: An apparatus includes an output bus configured to store data, a match table, one or more storage devices, and logic. The match table is configured to store a plurality of entries, each entry including a key value, wherein the match table specifies a matching entry in response to being queried by the query data. The one or more storage devices are configured to store operation information for each of the plurality of entries stored in the match table. The operation information specifies one or more instructions associated with each respective entry in the plurality of entries stored in the match table. The logic is configured to receive one or more operands from the output bus, identify one or more instructions from the one or more storage devices, and generate, based on the one or more instructions and the one or more operands, processed data.Type: GrantFiled: October 2, 2020Date of Patent: February 14, 2023Assignee: FUNGIBLE, INC.Inventors: Hariharan Lakshminarayanan Thantry, Srihari Raju Vegesna, Sureshkumar Nedunchezhian, Stimit Kishor Oak
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Patent number: 11218574Abstract: This disclosure describes techniques that include representing, traversing, and processing directed graphs using one or more content-addressable memory devices. In one example, this disclosure describes a method that includes presenting query data to one or more ternary content-addressable memory (TCAM) devices, wherein the query data includes state data and key data; receiving, from the TCAM devices, information about a matching address identified by the TCAM devices; accessing, based on the information about the matching address, information in one or more storage devices; performing, based on the information in the one or more storage devices, at least one operation on data included within the one or more storage devices to generate processed data; outputting the processed data; determining, based on the information in the one or more storage devices, new state data and a new key value; and presenting new query data to the TCAM devices.Type: GrantFiled: June 7, 2019Date of Patent: January 4, 2022Assignee: Fungible, Inc.Inventors: Hariharan Lakshminarayanan Thantry, Rohit Sunkam Ramanujam, John David Huber, Deepak Goel, Vikas Minglani
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Patent number: 11038993Abstract: Aspects of this disclosure describes techniques for parsing network packets, processing network packets, and modifying network packets before forwarding the modified network packets over a network. The present disclosure describes a system that, in some examples, parses network packets, generates data describing or specifying attributes of the network packet, identifies operations to be performed when processing a network packet, performs the identified operations, generates data describing or specifying how to modify and/or forward the network packet, modifies the network packet, and outputs the modified packet to another device or system, such as a switch.Type: GrantFiled: March 13, 2019Date of Patent: June 15, 2021Assignee: FUNGIBLE, INC.Inventors: Deepak Goel, Jean-Marc Frailong, Srihari Raju Vegesna, Stimit Kishor Oak, Rohit Sunkam Ramanujam, John David Huber, Hariharan Lakshminarayanan Thantry, Vikas Minglani, Saurin Patel, Sureshkumar Nedunchezhian
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Publication number: 20210103408Abstract: An apparatus includes an output bus configured to store data, a match table, one or more storage devices, and logic. The match table is configured to store a plurality of entries, each entry including a key value, wherein the match table specifies a matching entry in response to being queried by the query data. The one or more storage devices are configured to store operation information for each of the plurality of entries stored in the match table. The operation information specifies one or more instructions associated with each respective entry in the plurality of entries stored in the match table. The logic is configured to receive one or more operands from the output bus, identify one or more instructions from the one or more storage devices, and generate, based on the one or more instructions and the one or more operands, processed data.Type: ApplicationFiled: October 2, 2020Publication date: April 8, 2021Inventors: Hariharan Lakshminarayanan Thantry, Srihari Raju Vegesna, Sureshkumar Nedunchezhian, Stimit Kishor Oak
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Patent number: 10958770Abstract: This disclosure describes techniques that include storing, during parsing of a data unit or a network packet, information (i.e., “summary information”) that identifies how the network packet has been process and/or other aspects of the parsing process. In one example, this disclosure describes a method that includes parsing a packet header from a data unit, wherein parsing the packet header includes storing in result vector storage each of a plurality of data items derived from the packet header, the result vector storage having a result vector format defining fields within the result vector storage for storing each of the plurality of data items; storing in template storage, for each of the plurality of data items, summary information about the plurality of data items stored in the result vector storage; and processing, by the packet-processing integrated circuit and based on the summary information and the plurality of data items, the network packet.Type: GrantFiled: October 15, 2018Date of Patent: March 23, 2021Assignee: Fungible, Inc.Inventors: Hariharan Lakshminarayanan Thantry, Srihari Raju Vegesna, Stimit Kishor Oak, Vikas Minglani, Rohit Sunkam Ramanujam, John David Huber, Deepak Goel
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Publication number: 20200120191Abstract: This disclosure describes techniques that include storing, during parsing of a data unit or a network packet, information (i.e., “summary information”) that identifies how the network packet has been process and/or other aspects of the parsing process. In one example, this disclosure describes a method that includes parsing a packet header from a data unit, wherein parsing the packet header includes storing in result vector storage each of a plurality of data items derived from the packet header, the result vector storage having a result vector format defining fields within the result vector storage for storing each of the plurality of data items; storing in template storage, for each of the plurality of data items, summary information about the plurality of data items stored in the result vector storage; and processing, by the packet-processing integrated circuit and based on the summary information and the plurality of data items, the network packet.Type: ApplicationFiled: October 15, 2018Publication date: April 16, 2020Inventors: Hariharan Lakshminarayanan Thantry, Srihari Raju Vegesna, Stimit Kishor Oak, Vikas Minglani, Rohit Sunkam Ramanujam, John David Huber, Deepak Goel
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Publication number: 20190379770Abstract: This disclosure describes techniques that include representing, traversing, and processing directed graphs using one or more content-addressable memory devices. In one example, this disclosure describes a method that includes presenting query data to one or more ternary content-addressable memory (TCAM) devices, wherein the query data includes state data and key data; receiving, from the TCAM devices, information about a matching address identified by the TCAM devices; accessing, based on the information about the matching address, information in one or more storage devices; performing, based on the information in the one or more storage devices, at least one operation on data included within the one or more storage devices to generate processed data; outputting the processed data; determining, based on the information in the one or more storage devices, new state data and a new key value; and presenting new query data to the TCAM devices.Type: ApplicationFiled: June 7, 2019Publication date: December 12, 2019Inventors: Hariharan Lakshminarayanan Thantry, Rohit Sunkam Ramanujam, John David Huber, Deepak Goel, Vikas Minglani
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Publication number: 20190289102Abstract: Aspects of this disclosure describes techniques for parsing network packets, processing network packets, and modifying network packets before forwarding the modified network packets over a network. The present disclosure describes a system that, in some examples, parses network packets, generates data describing or specifying attributes of the network packet, identifies operations to be performed when processing a network packet, performs the identified operations, generates data describing or specifying how to modify and/or forward the network packet, modifies the network packet, and outputs the modified packet to another device or system, such as a switch.Type: ApplicationFiled: March 13, 2019Publication date: September 19, 2019Inventors: Deepak Goel, Jean-Marc Frailong, Srihari Raju Vegesna, Stimit Kishor Oak, Rohit Sunkam Ramanujam, John David Huber, Hariharan Lakshminarayanan Thantry, Vikas Minglani, Saurin Patel, Sureshkumar Nedunchezhian