Abstract: A tri-state NAND circuit includes a first input connected to receive a first input signal and a second input connected to receive a second input signal. The tri-state NAND circuit is connected to operate in accordance with a first clock signal and a second clock signal. A logic state of the second clock signal is opposite a logic state of the first clock signal. The tri-state NAND circuit is connected to transmit an output signal to a first node. A tri-state latch circuit is connected to hold a signal present at the first node in accordance with the first clock signal and the second clock signal. A pulse generating NAND circuit includes a first input connected to the first node and a second input connected to receive the first clock signal. The pulse generating NAND circuit is connected to transmit an output signal to a second node.

Abstract: A tri-state NAND circuit includes a first input connected to receive a first input signal and a second input connected to receive a second input signal. The tri-state NAND circuit is connected to operate in accordance with a first clock signal and a second clock signal. A logic state of the second clock signal is opposite a logic state of the first clock signal. The tri-state NAND circuit is connected to transmit an output signal to a first node. A tri-state latch circuit is connected to hold a signal present at the first node in accordance with the first clock signal and the second clock signal. A pulse generating NAND circuit includes a first input connected to the first node and a second input connected to receive the first clock signal. The pulse generating NAND circuit is connected to transmit an output signal to a second node.