Abstract: A system for calculating token rates for video encoding includes a plurality of different probability lookup tables implemented in hardware, wherein each of the probability lookup tables specifically corresponds to a different prediction mode of a video codec. The system includes an application-specific integrated circuit compute unit. For each candidate prediction mode among the different prediction modes, the application-specific integrated circuit is configured to determine a rate distortion cost (RD Cost) for a video. The application-specific integrated circuit is configured to select one of the plurality of different probability lookup tables that corresponds to the candidate prediction mode and use the selected one of the plurality of different probability lookup tables to calculate a corresponding token rate for the candidate prediction mode.

Abstract: A method for sharing the motion estimation and mode decision results and decisions of one codec with another codec is disclosed. A video is received to be transcoded into a plurality of different output encodings of a plurality of different codecs. Each codec has a different video encoding format. A shared motion estimation and a shared mode decision processing of the video are performed. One or more results of the shared mode decision processing shared across the plurality of different codecs are used to encode the video into the plurality of different output encodings of the plurality of different codecs.

Abstract: A video to be encoded using a codec is received. A first-pass analysis of the frames of the video is performed, including by collecting first-pass statistics data for each of the frames of the video. A specific frame of the video is selected for boosting an encoding rate of the specific frame. At least a portion of the first-pass statistics data is provided to a model to determine a boost factor for the specific frame. The encoding rate for the specific frame is determined using the boost factor.

Abstract: A hardware video processor comprises a cost calculation unit. The cost calculation unit is configured to determine rate distortion costs of a plurality of different modes for a portion of a video. The hardware video processor further comprises an evaluation unit. The evaluation unit is configured to receive the rate distortion costs of the plurality of different modes. At least one component of at least one of the rate distortion costs is adjusted based on a condition to determine at least one modified rate distortion cost of at least one of the plurality of different modes. The at least one modified rate distortion cost is used to evaluate the plurality of different modes and select one of the modes for use in encoding the portion of the video.

Abstract: A quantized transform coefficient matrix is partitioned into a sequence of partition portions. The coefficients of the matrix are grouped into the sequence of partition portions based on a hardware implemented scan order. Each partition portion is processed in an order of the sequence in a first pass. For each partition portion, a group of coefficients in the partition portion is determined. For each partition portion, a first data rate estimation for the quantized transform coefficient matrix is updated based on at least some coefficients of the group of coefficients in the partition portion and a maximum end-of-block. For each partition portion, an end-of-block estimation of the quantized transform coefficient matrix is updated based on at least some coefficients of the group of coefficients in the partition portion. A first resulting data rate estimation and a true end-of-block of the quantized transform coefficient matrix are determined after the first pass.

Abstract: A scalable hardware accelerator configured to compute video quality metrics is disclosed. In some embodiments, an accelerator for video quality metrics comprises an application-specific integrated circuit that includes a first scaling unit configured to scale a resolution of at least a portion of a reference frame of a video, a second scaling unit configured to scale a resolution of at least a portion of a distorted frame of a transcoded version of the video, and a kernel configured to compute a video quality metric for the distorted frame with respect to the reference frame using at least a first scaled output of the first scaling unit or a second scaled output of the second scaling unit.

Abstract: A scalable hardware accelerator configured to compute video quality metrics is disclosed. In some embodiments, an accelerator for video quality metrics comprises an application-specific integrated circuit that includes an interface configured to receive pixel data of a frame of a video being analyzed for quality metric determination and a kernel configured to compute a video quality metric for the received pixel data using a fixed-point hardware approximation of a floating-point based algorithm associated with the video quality metric.

Abstract: A scalable hardware accelerator configured to compute video quality metrics is disclosed. In some embodiments, an accelerator for video quality metrics comprises an application-specific integrated circuit that includes a buffer memory configured to store at least a portion of a reference frame of a video and at least a corresponding portion of a distorted frame of a transcoded version of the video and that includes a processing unit configured to receive data from the buffer memory and compute a perception-based video quality metric for the distorted frame with respect to the reference frame.

Abstract: Techniques to optimize memory reads when computing a video quality metric are disclosed. In some embodiments, an application-specific integrated circuit for computing video quality metrics includes a set of caches configured to store neighbor pixel data for edge width searches of pixels comprising a frame of a video being analyzed for a video quality metric and a kernel configured to receive corresponding neighbor pixel data for pixels comprising a current processing block of the frame from a subset of the set of caches and simultaneously perform edge width searches for pixels comprising the current processing block to determine corresponding pixel edge width values used for computing the video quality metric.

Abstract: A system comprises a source block buffer and a plurality of hardware motion estimation search processing units in communication with the source block buffer. The source block buffer is configured to store at least a portion of a source block of a source frame of a video. The plurality of hardware motion estimation search processing units are configured to perform at least a portion of a motion estimation for the source block at least in part in parallel across a plurality of different reference frames of the video. Each of the hardware motion estimation search processing units is configured to be assigned a different one of the plurality of different reference frames and is configured to compare at least the portion of the source block with a portion of the assigned one of the different reference frames.

Abstract: A method for sharing the motion estimation and mode decision results and decisions of one codec with another codec is disclosed. A video is received to be transcoded into a plurality of different output encodings of a plurality of different codecs. Each codec has a different video encoding format. A shared motion estimation and a shared mode decision processing of the video are performed. One or more results of the shared mode decision processing shared across the plurality of different codecs are used to encode the video into the plurality of different output encodings of the plurality of different codecs.

Abstract: The disclosed may include various systems and methods for improving the efficiency and scalability of large-scale systems. For example, the disclosed may include systems and methods for automatic privacy enforcement using privacy-aware infrastructure, scalable general-purpose low cost integer motion search, efficient scaler filter coefficients layout for flexible scaling quality control with limited hardware resources, hardware optimization for power saving with both different codecs enabled, optimizing storage overhead and performance for large distributed data warehouse, mass and volume efficient integration of intersatellite link terminals to a satellite bus, and overcoming retention limit for memory-based distributed database systems.

Abstract: The present invention facilitates efficient and effective detection of pixel alteration. The number and configuration of pixels in a block partition can be flexibly changed. The filter inputs in the multi-protocol filter can be flexibly changed to meet the deblocking requirement in the target video compression standard. In one embodiment, the deblock engine includes an input interface, a neighbor buffer, a current data buffer; and a multi-protocol filter. The input interface receives reconstructed data. The neighbor buffer temporarily stores neighbor information. The current data buffer receives the reconstructed data and the neighbor information. The multi-protocol filter filters information selected from the reconstructed data and neighbor information.

Abstract: In one example, a method of encoding video data includes allocating, based on a complexity of a reference frame and a quantity of bits allocated to a current frame, a quantity of bits to a current largest coding unit (LCU) included in the current frame. In this example, the method also includes determining, based on the quantity of bits allocated to the current LCU, a quantization parameter (QP) for the current LCU, and encoding the current LCU with the determined QP.

Abstract: A system for executing video encoding operations. The system includes a video encoder for encoding an incoming video stream into a plurality of macro blocks. A motion estimation engine is coupled to the video encoder for controlling the encoding of the macro blocks. A video rate control processor is coupled to the video encoder and coupled to the motion estimation engine. The video rate control processor receives a plurality of parameters from the video encoder that indicate an encoding complexity for a macro block and a video frame of the video stream and, upon receiving an indication from the motion estimation engine, computes a quantization parameter for the macro block. The quantization parameter is dynamically adjusted for the video stream to achieve a target bit rate.

Abstract: An encoder provided according to an aspect of the present invention uses different encoding techniques depending on an amount of power available in the corresponding durations. Due to the ability to use such different encoding techniques, power may be optimally utilized. The optimization is further enhanced by dynamically switching between encoding techniques according to power amount availability in corresponding durations. In an embodiment, each encoding technique estimates motion vectors at corresponding level of precision (thereby consuming a corresponding level of power) and the precision level is chosen to correspond to available power budget. The circuitry not required for a desired precision level may be switched off.

Abstract: The present invention facilitates efficient and effective detection of pixel alteration. The number and configuration of pixels in a block partition can be flexibly changed. The filter inputs in the multi-protocol filter can be flexibly changed to meet the deblocking requirement in the target video compression standard. In one embodiment, the deblock engine includes an input interface, a neighbor buffer, a current data buffer; and a multi-protocol filter. The input interface receives reconstructed data. The neighbor buffer temporarily stores neighbor information. The current data buffer receives the reconstructed data and the neighbor information. The multi-protocol filter filters information selected from the reconstructed data and neighbor information.

Abstract: An encoder provided according to an aspect of the present invention uses different encoding techniques depending on an amount of power available in the corresponding durations. Due to the ability to use such different encoding techniques, power may be optimally utilized. The optimization is further enhanced by dynamically switching between encoding techniques according to power amount availability in corresponding durations. In an embodiment, each encoding technique estimates motion vectors at corresponding level of precision (thereby consuming a corresponding level of power) and the precision level is chosen to correspond to available power budget. The circuitry not required for a desired precision level may be switched off.

Abstract: A system for executing video encoding operations. The system includes a video encoder for encoding an incoming video stream into a plurality of macro blocks. A motion estimation engine is coupled to the video encoder for controlling the encoding of the macro blocks. A video rate control processor is coupled to the video encoder and coupled to the motion estimation engine. The video rate control processor receives a plurality of parameters from the video encoder that indicate an encoding complexity for a macro block and a video frame of the video stream and, upon receiving an indication from the motion estimation engine, computes a quantization parameter for the macro block. The quantization parameter is dynamically adjusted for the video stream to achieve a target bit rate.