Patents by Inventor Harikrishna P

Harikrishna P has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Voltage regulator with saturation prevention
    Patent number: 12645235
    Abstract: In described examples, a low dropout voltage regulator includes an input voltage terminal, a resistive element, first and second transistors, an output terminal, a differential amplifier, and first and second saturation prevention circuits. The resistive element is coupled between the input voltage terminal and a gate of the first transistor. The output terminal is coupled to the drain of the first transistor and the source of the second transistor. A first input of the differential amplifier receives a reference voltage, and a second input is coupled to the output terminal. The first saturation prevention circuit provides a first clamp current to the differential amplifier output if the gate-source voltage of the first transistor is less than a first threshold voltage. The second saturation prevention circuit provides a second clamp current to the differential amplifier output if the gate-source voltage of the second transistor is greater than a second threshold voltage.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: June 2, 2026
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rinu Mathew, Harikrishna P, Venkatesh Kadlimatti
  • VOLTAGE GLITCH DETECTOR
    Publication number: 20250348102
    Abstract: In described examples, a voltage glitch detector includes a current source, a latch, and first, second, third, fourth, and fifth transistors. A source of the third transistor is coupled to a source of the second transistor, and a gate and drain of the third transistor is coupled to gates of the first and second transistors and a first terminal of the current source. A drain of the fourth transistor is coupled to a drain of the first transistor and an input of the latch. A source of the fifth transistor is coupled to a source of the fourth transistor and the second terminal of the current source. A gate and drain of the fifth transistor is coupled to a gate of the fourth transistor and a drain of the second transistor.
    Type: Application
    Filed: July 22, 2025
    Publication date: November 13, 2025
    Inventors: Venkatesh Kadlimatti, Aritra Chowdhury, Harikrishna P
  • Voltage glitch detector
    Patent number: 12366876
    Abstract: In described examples, a voltage glitch detector includes a current source, a latch, and first, second, third, fourth, and fifth transistors. A source of the third transistor is coupled to a source of the second transistor, and a gate and drain of the third transistor is coupled to gates of the first and second transistors and a first terminal of the current source. A drain of the fourth transistor is coupled to a drain of the first transistor and an input of the latch. A source of the fifth transistor is coupled to a source of the fourth transistor and the second terminal of the current source. A gate and drain of the fifth transistor is coupled to a gate of the fourth transistor and a drain of the second transistor.
    Type: Grant
    Filed: April 28, 2023
    Date of Patent: July 22, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Venkatesh Kadlimatti, Aritra Chowdhury, Harikrishna P
  • VOLTAGE GLITCH DETECTOR
    Publication number: 20240361794
    Abstract: In described examples, a voltage glitch detector includes a current source, a latch, and first, second, third, fourth, and fifth transistors. A source of the third transistor is coupled to a source of the second transistor, and a gate and drain of the third transistor is coupled to gates of the first and second transistors and a first terminal of the current source. A drain of the fourth transistor is coupled to a drain of the first transistor and an input of the latch. A source of the fifth transistor is coupled to a source of the fourth transistor and the second terminal of the current source. A gate and drain of the fifth transistor is coupled to a gate of the fourth transistor and a drain of the second transistor.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Venkatesh Kadlimatti, Aritra Chowdhury, Harikrishna P
  • VOLTAGE REGULATOR WITH SATURATION PREVENTION
    Publication number: 20230152828
    Abstract: In described examples, a low dropout voltage regulator includes an input voltage terminal, a resistive element, first and second transistors, an output terminal, a differential amplifier, and first and second saturation prevention circuits. The resistive element is coupled between the input voltage terminal and a gate of the first transistor. The output terminal is coupled to the drain of the first transistor and the source of the second transistor. A first input of the differential amplifier receives a reference voltage, and a second input is coupled to the output terminal. The first saturation prevention circuit provides a first clamp current to the differential amplifier output if the gate-source voltage of the first transistor is less than a first threshold voltage. The second saturation prevention circuit provides a second clamp current to the differential amplifier output if the gate-source voltage of the second transistor is greater than a second threshold voltage.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 18, 2023
    Inventors: Rinu Mathew, Harikrishna P, Venkatesh Kadlimatti