Abstract: Operating pulsed latches on a variable power supply including turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch; turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch; performing a scan operation using the first latch and the second latch; turning off the first power rail powering the first latch; and performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation.

Abstract: Operating pulsed latches on a variable power supply including turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch; turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch; performing a scan operation using the first latch and the second latch; turning off the first power rail powering the first latch; and performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation.

Abstract: Operating pulsed latches on a variable power supply including turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch; turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch; performing a scan operation using the first latch and the second latch; turning off the first power rail powering the first latch; and performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation.

Abstract: Operating pulsed latches on a variable power supply including turning on a first power rail powering a first latch of an integrated circuit, wherein the first latch is a pulsed latch; turning on a second power rail powering a second latch of the integrated circuit, wherein the second latch is operatively coupled to the first latch; performing a scan operation using the first latch and the second latch; turning off the first power rail powering the first latch; and performing a functional operation using the second latch, wherein the first power rail powering the first latch is off during the functional operation.

Abstract: Crosstalk effects can be taken into account in automatic test pattern generation (ATPG) by providing crosstalk fault models, determining paths and/or nodes to be sensitized to activate each crosstalk fault, and optimizing to enable as many crosstalk faults as possible with a given pattern, subject to constraints. Constraints can include threshold numbers of endpoints/observation points and/or attempts to sensitize. Intermediate nodes in a crosstalk fault model path to an observation point can also be determined and/or sensitized.

Abstract: Crosstalk effects can be taken into account in automatic test pattern generation (ATPG) by providing crosstalk fault models, determining paths and/or nodes to be sensitized to activate each crosstalk fault, and optimizing to enable as many crosstalk faults as possible with a given pattern, subject to constraints. Constraints can include threshold numbers of endpoints/observation points and/or attempts to sensitize. Intermediate nodes in a crosstalk fault model path to an observation point can also be determined and/or sensitized.

Abstract: A method is disclosed for programming an ID register of a microchip. The method comprises the step, prior to packaging, of attaching at least one additional ID pin to the die of the microchip. The at least one pin being so attached that, when the microchip is packaged, the at least one pin is sealed within the package. At least a portion of the microchip identity data is programmed by providing a plurality of unique combinations of binary data to the at least one additional pin. Each unique combination of binary data corresponds to a unique identity of the microchip. The at least one pin is coupled to a respective module of the microchip layout for providing, via the at least one pin, information associated with the particular identity of the microchip. The at least one pin is also coupled to the identification register, so as to, upon testing, include the respective combination of binary data in the ID register data of the microchip.

Abstract: A method is disclosed for programming an ID register of a microchip. The method comprises the step, prior to packaging, of attaching at least one additional ID pin to the die of the microchip. The at least one pin being so attached that, when the microchip is packaged, the at least one pin is sealed within the package. At least a portion of the microchip identity data is programmed by providing a plurality of unique combinations of binary data to the at least one additional pin. Each unique combination of binary data corresponds to a unique identity of the microchip. The at least one pin is coupled to a respective module of the microchip layout for providing, via the at least one pin, information associated with the particular identity of the microchip. The at least one pin is also coupled to the identification register, so as to, upon testing, include the respective combination of binary data in the ID register data of the microchip.