Patents by Inventor Harinarayanan Seshadri
Harinarayanan Seshadri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11768533Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: GrantFiled: August 2, 2022Date of Patent: September 26, 2023Assignee: Tahoe Research, Ltd.Inventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Publication number: 20230221786Abstract: Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.Type: ApplicationFiled: March 8, 2023Publication date: July 13, 2023Applicant: Tahoe Research, Ltd.Inventors: Barnes COOPER, Harinarayanan SESHADRI, Rajeev MURALIDHAR, Noor MUBEEN
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Patent number: 11687142Abstract: Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack. An apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have a plurality of memory registers. The second circuitry may be operable to establish values for a plurality of features based on samples of values of the plurality of memory registers taken at one or more times within a range of time of predetermined length. The third circuitry may be operable to compare the plurality of features against a plurality of learned parameters for a reference workload.Type: GrantFiled: June 14, 2021Date of Patent: June 27, 2023Assignee: Intel CorporationInventors: Shravan Kumar Belagal Math, Noor Mubeen, Harinarayanan Seshadri
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Patent number: 11604504Abstract: Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.Type: GrantFiled: September 21, 2021Date of Patent: March 14, 2023Assignee: Tahoe Research, Ltd.Inventors: Barnes Cooper, Harinarayanan Seshadri, Rajeev Muralidhar, Noor Mubeen
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Publication number: 20230004209Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: ApplicationFiled: August 2, 2022Publication date: January 5, 2023Applicant: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe FIAT, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 11422615Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: GrantFiled: January 13, 2020Date of Patent: August 23, 2022Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Publication number: 20220026974Abstract: Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.Type: ApplicationFiled: September 21, 2021Publication date: January 27, 2022Inventors: BARNES COOPER, HARINARAYANAN SESHADRI, RAJEEV MURALIDHAR, NOOR MUBEEN
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Publication number: 20210311538Abstract: Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack. An apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have a plurality of memory registers. The second circuitry may be operable to establish values for a plurality of features based on samples of values of the plurality of memory registers taken at one or more times within a range of time of predetermined length. The third circuitry may be operable to compare the plurality of features against a plurality of learned parameters for a reference workload.Type: ApplicationFiled: June 14, 2021Publication date: October 7, 2021Applicant: Intel CorporationInventors: Shravan Kumar Belagal Math, Noor Mubeen, Harinarayanan Seshadri
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Patent number: 11132046Abstract: Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.Type: GrantFiled: December 15, 2017Date of Patent: September 28, 2021Assignee: Intel CorporationInventors: Barnes Cooper, Harinarayanan Seshadri, Rajeev Muralidhar, Noor Mubeen
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Publication number: 20210208663Abstract: Power governance circuitry is provided to control a performance level of a processing unit of a processing platform. The power governance circuitry comprises measurement circuitry to measure a current utilization of the processing unit at a current operating frequency and to determine any change in utilization or power and frequency control circuitry is provided to update the current operating frequency to a new operating frequency by determining a new target quantified power expenditure to be applied in a subsequent processing cycle depending on the determination of any change in utilization or power. A new operating frequency is selected to satisfy the new target quantified power based on a scalability function specifying a variation of a given value of utilization or power with the operating frequency. A processing platform and machine readable instructions are provided to set a new quantified target power of a processing unit.Type: ApplicationFiled: December 15, 2017Publication date: July 8, 2021Inventors: BARNES COOPER, HARINARAYANAN SESHADRI, RAJEEV MURALIDHAR, NOOR MUBEEN
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Patent number: 11036275Abstract: Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack. An apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have a plurality of memory registers. The second circuitry may be operable to establish values for a plurality of features based on samples of values of the plurality of memory registers taken at one or more times within a range of time of predetermined length. The third circuitry may be operable to compare the plurality of features against a plurality of learned parameters for a reference workload.Type: GrantFiled: March 29, 2019Date of Patent: June 15, 2021Assignee: Intel CorporationInventors: Shravan Kumar Belagal Math, Noor Mubeen, Harinarayanan Seshadri
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Publication number: 20200310510Abstract: Described are mechanisms and methods for applying Machine Learning (ML) techniques for power management at different levels of a power management stack. An apparatus may comprise a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have a plurality of memory registers. The second circuitry may be operable to establish values for a plurality of features based on samples of values of the plurality of memory registers taken at one or more times within a range of time of predetermined length. The third circuitry may be operable to compare the plurality of features against a plurality of learned parameters for a reference workload.Type: ApplicationFiled: March 29, 2019Publication date: October 1, 2020Inventors: Shravan Kumar BELAGAL MATH, Noor MUBEEN, Harinarayanan SESHADRI
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Patent number: 10768680Abstract: Methods and apparatuses relating to transactional power management are described. In one embodiment, a hardware apparatus includes a hardware processor having a core, a plurality of power domains to transition to one of a plurality of power states in response to a power management command for each power domain, and a power transaction unit to assign a first power management command as a first power transaction and a second power management command as a second power transaction for concurrent execution, perform a commit of the first power transaction and the second power transaction when there is no conflict between the first power transaction and the second power transaction, and perform an abort of the first power transaction and a commit of the second power transaction when there is a conflict between the first power transaction and the second power transaction.Type: GrantFiled: August 15, 2017Date of Patent: September 8, 2020Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Nivedha Krishnakumar, Youvedeep Singh, Suketu R. Partiwala
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Publication number: 20200272219Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: ApplicationFiled: January 13, 2020Publication date: August 27, 2020Applicant: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe FIAT, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 10671404Abstract: Dynamic power management of integrated devices can be accomplished using game theory. In an example, power demands for individual devices (e.g., CPU, GPU, communications, etc.) can be controlled by governors. An engine can determine a system condition (e.g., docked or undocked) and use a reward and/or penalty matrix to determine power settings to provide to governors. Periodically, the engine can reevaluate the system condition and power settings for the governors. For example, device components can be modeled as players in a game. In the case of idle power management scenarios, the players can deploy cooperative gaming strategy to allow the system to be in a low power state.Type: GrantFiled: February 14, 2018Date of Patent: June 2, 2020Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri
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Patent number: 10564705Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: GrantFiled: May 18, 2018Date of Patent: February 18, 2020Assignee: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe Fiat, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 10551900Abstract: A first optimal CPU frequency that produces minimal power consumption for a CPU/platform combination may be calculated by using an Efficiency Aware Race to Halt (EARtH) algorithm, which ignores the power efficiency curve of the voltage regulator (VR). These results may then be modified by applying the power efficiency curve of the associated VR to determine a second optimal CPU frequency that produces power consumption that is less than the value calculated by the EARtH algorithm.Type: GrantFiled: March 28, 2017Date of Patent: February 4, 2020Assignee: Intel CorporationInventors: Vijayakumar A. Dibbad, Satish Prathaban, Harinarayanan Seshadri, Rajeev D. Muralidhar
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Publication number: 20180364792Abstract: Methods and apparatus relating to platform power consumption reduction via power state switching are described. In one embodiment, control logic causes a processor to enter a first low power consumption state (e.g., S0ix) instead of a second low power consumption state (e.g., S3) based on whether a threshold time period exists between a first wake event (e.g., corresponding to a first one of one or more awake requests) and a second wake event (e.g., corresponding to a second one of the one or more awake requests). Other embodiments are also claimed and disclosed.Type: ApplicationFiled: May 18, 2018Publication date: December 20, 2018Applicant: Intel CorporationInventors: Rajeev D. Muralidhar, Harinarayanan Seshadri, Vishwesh M. Rudramuni, Richard Quinzio, Christophe FIAT, Aymen Zayet, Youvedeep Singh, Illyas M. Mansoor
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Patent number: 10133336Abstract: Systems and methods may provide for identifying runtime information associated with an active workload of a platform, and making an active idle state determination for the platform based on at least in part the runtime information. In addition, a low power state of a shared resource on the platform may be controlled concurrently with an execution of the active workload based on at least in part the active idle state determination.Type: GrantFiled: November 27, 2012Date of Patent: November 20, 2018Assignee: Intel CorporationInventors: Ren Wang, Tsung-Yuan C. Tai, Jr-Shian Tsai, Bruce L. Fleming, Rajeev D. Muralidhar, Mesut A. Ergin, Prakash N. Iyer, Harinarayanan Seshadri
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Publication number: 20180284863Abstract: A first optimal CPU frequency that produces minimal power consumption for a CPU/platform combination may be calculated by using an Efficiency Aware Race to Halt (EARtH) algorithm, which ignores the power efficiency curve of the voltage regulator (VR). These results may then be modified by applying the power efficiency curve of the associated VR to determine a second optimal CPU frequency that produces power consumption that is less than the value calculated by the EARtH algorithm.Type: ApplicationFiled: March 28, 2017Publication date: October 4, 2018Applicant: Intel CorporationInventors: Vijayakumar A. Dibbad, Satish Prathaban, Harinarayanan Seshadri, Rajeev D. Muralidhar