Patents by Inventor Harindranath Parmeswaran

Harindranath Parmeswaran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods, systems, and apparatus for variation aware extracted timing models
    Patent number: 8239798
    Abstract: In one embodiment of the invention, a method of analysis of a circuit design is disclosed to generate a statistical timing model. The method includes receiving a timing graph of a circuit including arcs with a statistical function of delay, slew, or arrival time; determining primary input ports and output ports of the circuit; identifying timing pins between the input ports and the output ports of the circuit; and evaluating the timing pins from input ports to output ports to reduce the timing graph to ease analysis of the reduced timing graph with a processor.
    Type: Grant
    Filed: August 2, 2008
    Date of Patent: August 7, 2012
    Assignee: Cadence Design Systems, Inc.
    Inventors: Ratnakar Goyal, Naresh Kumar, Harindranath Parmeswaran