Abstract: System and method embodiments are disclosed for high availability management for open radio access network (O-RAN). The O-RAN may be deployed on cloud with the O-CU deployed on a region cloud, O-RUs deployed on a cell site O-Cloud, and O-DUs deployed on an edge cloud. Each O-RU may comprise one or more RF clusters, computation clusters, and interface clusters. O-RU instances and O-DU instances may be instantiated with redundancy on the cell site O-Cloud and on the edge cloud, respectively, to serve one or more users. Local and central high-availability (HA) managers may be used to monitor O-RU instance performance for failure prediction/detection and to monitor internal states of each O-DU instance. In response to O-RU instance failure or O-DU internal states beyond/below state thresholds, new O-RU or O-DU instances may be instantiated as replacement instances for O-Cloud high availability management.

Abstract: With advanced compute capabilities and growing convergence of wireless standards, it is desirable to run multiple wireless standards, e.g., 4G, 5G NR, and Wi-Fi, on a single signal processing system. In the present disclosure, two baseband processors are used with each processor dedicated for one type of signal processing, such as 5G or Wi-Fi. The two baseband processors are interlinked via a chip-to-chip interconnect link for ingress and egress data transfer between the two processors. These two processors share an Ethernet link for benefits including cost saving, reduction in overall chipset power, and reduced form factor of the enclosure. Application of the disclosed embodiments may realize concurrent 5G Fronthaul and Wi-Fi traffic processing on the same Ethernet link. Such an application may be applied to other related scenarios, including Ethernet link sharing for dual Wi-Fi baseband processors, and Ethernet link sharing for Wi-Fi and gNodeB deployments, etc.

Abstract: With advanced compute capabilities and growing convergence of wireless standards, it is desirable to run multiple wireless standards, e.g., 4G, 5G NR, and Wi-Fi, on a single signal processing system. In the present disclosure, two baseband processors are used with each processor dedicated for one type of signal processing, such as 5G or Wi-Fi. The two baseband processors are interlinked via a chip-to-chip interconnect link for ingress and egress data transfer between the two processors. These two processors share an Ethernet link for benefits including cost saving, reduction in overall chipset power, and reduced form factor of the enclosure. Application of the disclosed embodiments may realize concurrent 5G Fronthaul and Wi-Fi traffic processing on the same Ethernet link. Such an application may be applied to other related scenarios, including Ethernet link sharing for dual Wi-Fi baseband processors, and Ethernet link sharing for Wi-Fi and gNodeB deployments, etc.

Abstract: Advances in wireless technologies have resulted in the ability of a wireless communication system to support wireless communications of different standards, e.g., 5G, LTE, and Wi-Fi. Different Wireless standards have aspects which are very different from each other. Described in the present disclosure are embodiments of architecture with hardware and software split to allow implementation of different wireless standards along a configurable signal process path. The configurable signal process path comprises software configurable operators that may be configured in a desired level of granularity to load desirable software to process signals of various standards on the same hardware. Embodiments of the disclosed architecture with hybrid hardware and software implementation may improve system operation efficiency and lower system complexity to serve communications across multiple wireless standards.

Abstract: A wireless communication device is disclosed that is capable of reduced power consumption. Uplink and downlink sub-frames in a WiMAX, 802.16m or LTE environment often include several vacant symbols during which power-hungry hardware and software components need not operate at full power. By analyzing a physical layer beacon and control information of a received signal, the specific locations of data bursts can be determined, as well as periods of needed operation of a receiver module to effectively decode those data bursts. The receiver module can otherwise be controlled to operate in a LOW power state during remaining periods of vacant time, thereby conserving power consumption and extending battery life.

Abstract: A wireless communication device is disclosed that is capable of reduced power consumption. Uplink and downlink sub-frames in a WiMAX, 802.16m or LTE environment often include several vacant symbols during which power-hungry hardware and software components need not operate at full power. By analyzing a physical layer beacon and control information of a received signal, the specific locations of data bursts can be determined, as well as periods of needed operation of a receiver module to effectively decode those data bursts. The receiver module can otherwise be controlled to operate in a LOW power state during remaining periods of vacant time, thereby conserving power consumption and extending battery life.

Abstract: A method and apparatus for buffering an encoded signal having a plurality of codewords for a turbo decoder is provided. The method comprises de-interleaving each sub-block of the codeword received at the turbo-decoder; and storing LLRs of the de-interleaved codeword LLRs into an input buffer. Thereafter, each of punctured locations, if any, in the de-interleaved codeword is indicated to a read logic for enabling the latter to fill in each of those locations with a pre-determined LLR value as and when a read request corresponding to one of those locations arrives. This method obviates the need for storing the pre-determined LLRs at the punctured locations into the input buffer and thereby cuts down the input latency of turbo decoder significantly for higher code rates.

Abstract: A method and apparatus for buffering an encoded signal having a plurality of codewords for a turbo decoder is provided. The method comprises de-interleaving each sub-block of the codeword received at the turbo-decoder; and storing LLRs of the de-interleaved codeword LLRs into an input buffer. Thereafter, each of punctured locations, if any, in the de-interleaved codeword is indicated to a read logic for enabling the latter to fill in each of those locations with a pre-determined LLR value as and when a read request corresponding to one of those locations arrives. This method obviates the need for storing the pre-determined LLRs at the punctured locations into the input buffer and thereby cuts down the input latency of turbo decoder significantly for higher code rates.

Abstract: In one embodiment, the invention is an apparatus for assembling data for virtual concatenation. The apparatus includes an auxiliary memory having a set of storage locations for data. The apparatus also includes an external memory having a set of storage locations for data. The apparatus further includes a data assembler coupled to the auxiliary memory and the external memory. The data assembler is to read data of a virtual container from the external memory. The data assembler is also to store data of the virtual container in the auxiliary memory. The data assembler is further to determine if all data of the virtual container is present in the auxiliary memory. The data assembler is also to generate a set of addresses of the data of the virtual container in the auxiliary memory. The data assembler is further to read the data of the virtual container from the auxiliary memory. The data assembler is also to interleave the data of the virtual container.

Abstract: In one embodiment, the invention is an apparatus for testing differential delay correction of network elements using virtual concatenation. The apparatus includes a first PRBS (pseudo-random bit stream) generator dedicated to a first tributary. The apparatus also includes an interface between the first PRBS generator and a tester. The apparatus further includes an interface between the first PRBS generator and a device under test. The apparatus may further include a second PRBS dedicated to a second tributary. The apparatus may also include a control logic block to control the first PRBS generator and the second PRBS generator, and coupled to the first PRBS generator and the second PRBS generator.