Patents by Inventor Haris Basit

Haris Basit has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220418113
    Abstract: Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject matter further discloses methods of electrolytic plating by controlling surface area of an anode.
    Type: Application
    Filed: August 26, 2022
    Publication date: December 29, 2022
    Inventors: Michael Riley Vinson, Sunity K. Sharma, Haris Basit, Shinichi Iketani
  • Publication number: 20210345498
    Abstract: Devices, methods, and systems for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Inventors: Shinichi IKETANI, Michael Riley VINSON, Haris BASIT
  • Publication number: 20210265716
    Abstract: Systems, methods, and devices related to hollow metallic objects are disclosed. A solid sacrificial material is formed in a desired three-dimensional shape, and a precursor is deposited about an exterior surface of the solid sacrificial material. The precursor is used to deposit a first conductor about the exterior surface of the solid sacrificial material, and the solid sacrificial material is then removed. The first conductor assumes the three-dimensional shape, and is substantially hollow after removing the solid sacrificial material. Contemplated hollow metallic objects include waveguides, heat pipes, and vapor chambers.
    Type: Application
    Filed: February 19, 2021
    Publication date: August 26, 2021
    Inventors: Haris BASIT, Michael Riley VINSON
  • Patent number: 11076492
    Abstract: Devices, methods, and systems for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: July 27, 2021
    Assignee: Averatek Corporation
    Inventors: Shinichi Iketani, Michael Riley Vinson, Haris Basit
  • Publication number: 20210045252
    Abstract: Various inventions are disclosed in the microchip manufacturing arts. Conductive pattern formation by semi-additive processes are disclosed. Further conductive patterns and methods using activated precursors are also disclosed. Aluminum laminated surfaces and methods of circuit formation therefrom are further disclosed. Circuits formed on an aluminum heat sink are also disclosed. The inventive subject mater further discloses methods of electrolytic plating by controlling surface area of an anode.
    Type: Application
    Filed: April 10, 2020
    Publication date: February 11, 2021
    Inventors: Haris BASIT, Michael Riley VINSON, Sunity K. SHARMA, Shinichi IKETANI, Divyakant KADIWALA
  • Publication number: 20200196456
    Abstract: Devices, methods, and systems for forming an electrical circuit out of a conductor embedded in two layers of substrate are disclosed. Portions of the two layers of substrate and the conductor are removed, forming a cavity through the two layers and the conductor. A blocker material is deposited along the wall of the cavity. A portion of the blocker material and adjacent layer of the substrate is removed forming another cavity in contact with a part of the conductor. A surface of the second cavity is then electroless plated by a conductive metal to form part of the electrical circuit.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 18, 2020
    Inventors: Shinichi IKETANI, Michael Riley VINSON, Haris BASIT
  • Publication number: 20200120811
    Abstract: Methods and systems are contemplated for making portions of electrical circuits with embedded electrical components, and the electrical circuits produced thereby. A layer of dielectric material is deposited over a substrate, and a cavity is formed in the dielectric material. An electrical component (e.g., integrated chip, etc.) is deposited in the cavity and covered by a further dielectric material, embedding the electrical component. Another cavity is formed in the further dielectric material, and a catalyst (e.g., electrolytic deposition catalyst, electroless deposition catalyst, etc.) is deposited over the further dielectric material and at least a portion of the electrical component. A conductor is then plated at the catalyst, preferably contacting the I/O ports of the electrical component.
    Type: Application
    Filed: October 16, 2019
    Publication date: April 16, 2020
    Inventors: Haris BASIT, Michael Riley VINSON, Steve IKETANI
  • Publication number: 20190244726
    Abstract: A cable for propagating high frequency signals comprises a first insulated hollow conductor and a second insulated hollow conductor in a braided arrangement to form the cable. The braided arrangement distributes the first and second hollow conductors such that the cable is equalized.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 8, 2019
    Inventor: Haris Basit
  • Patent number: 8629807
    Abstract: Local oscillator circuitry for an antenna array is disclosed. The circuitry includes an array of rotary traveling wave oscillators which are arranged in a pattern over an area and coupled so as to make them coherent. This provides for a set of phase synchronous local oscillators distributed over a large area. The array also includes a plurality of phase shifters each of which is connected to one of the rotary oscillators to provide a phase shifted local oscillator for the array. The phase shifter optionally includes a cycle counter that is configured to count cycles of the rotary oscillator to which it is connected and control circuitry that is then operative to provide a shifted rotary oscillator output based on the count from the cycle counter.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: January 14, 2014
    Assignee: Analog Devices, Inc.
    Inventors: John Wood, Haris Basit
  • Publication number: 20120039366
    Abstract: Local oscillator circuitry for an antenna array is disclosed. The circuitry includes an array of rotary traveling wave oscillators which are arranged in a pattern over an area and coupled so as to make them coherent. This provides for a set of phase synchronous local oscillators distributed over a large area. The array also includes a plurality of phase shifters each of which is connected to one of the rotary oscillators to provide a phase shifted local oscillator for the array. The phase shifter optionally includes a cycle counter that is configured to count cycles of the rotary oscillator to which it is connected and control circuitry that is then operative to provide a shifted rotary oscillator output based on the count from the cycle counter. A system and method for operating a true-time delay phased array antenna system. The system includes a plurality of antenna element circuits for driving or receiving an rf signal from the elements of the array.
    Type: Application
    Filed: June 6, 2006
    Publication date: February 16, 2012
    Applicant: MOBIUS POWER, LLC
    Inventors: John Wood, Haris Basit