Patents by Inventor Haris Lekatsas
Haris Lekatsas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7474750Abstract: An architecture for content-aware compression and/or encryption of various segments of a application is disclosed. The architecture advantageously allows decompression and decryption units to be placed various levels of a memory hierarchy.Type: GrantFiled: June 16, 2004Date of Patent: January 6, 2009Assignee: NEC Laboratories America, Inc.Inventors: Haris Lekatsas, Joerg Henkel, Srimat Chakradhar, Venkata Jakkula
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Patent number: 7302543Abstract: An embedded systems architecture is disclosed which can flexibly handle compression of both instruction code and data.Type: GrantFiled: June 16, 2004Date of Patent: November 27, 2007Assignee: NEC Laboratories America, Inc.Inventors: Haris Lekatsas, Joerg Henkel, Srimat Chakradhar, Venkata Jakkula
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Patent number: 7203935Abstract: A method for code compression of a program, the method comprising separating code from data. Software transformations necessary to make address mappings between compressed and uncompressed space are introduced into the code. Statistics are obtained about frequency of occurrence instructions, wherein said statistics include frequency of occurrence of two consecutive instructions. The program is parsed to identify occurrence of instructions or instruction pairs. The identified instructions are replaced with an address to a compressed bus-word table. An address mapping is generated from uncompressed address to compressed addresses.Type: GrantFiled: December 5, 2002Date of Patent: April 10, 2007Assignee: NEC CorporationInventors: Srimat Chakradhar, Jörg Henkel, Venkata Jakkula, Haris Lekatsas, Murugan Sankaradass
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Publication number: 20070005911Abstract: A dynamic memory compression architecture is disclosed which allows applications with working data sets exceeding the physical memory of an embedded system to still execute correctly. The dynamic memory compression architecture provides “on-the-fly” compression and decompression of the working data in a manner which is transparent to the user and which does not require special-purpose hardware. A new compression technique is also herein disclosed which is particularly advantageous when utilized with the above-mentioned dynamic memory compression architecture.Type: ApplicationFiled: June 30, 2006Publication date: January 4, 2007Applicants: NEC LABORATORIES AMERICA, INC., NORTHWESTERN UNIVERSITYInventors: Lei Yang, Haris Lekatsas, Robert Dick, Srimat Chakradhar
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Publication number: 20070005625Abstract: A storage management architecture is disclosed which is particularly advantageous for devices such as embedded systems. The architecture provides a framework for a compression/decompression system which advantageously is software-based and which facilitates the compression of both instruction code and writeable data.Type: ApplicationFiled: September 21, 2005Publication date: January 4, 2007Applicant: NEC Laboratories America, Inc.Inventors: Haris Lekatsas, Srimat Chakradhar
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Publication number: 20060101223Abstract: An embedded systems architecture is disclosed which can flexibly handle compression of both instruction code and data.Type: ApplicationFiled: June 16, 2004Publication date: May 11, 2006Applicant: NEC Laboratories America, Inc.Inventors: Haris Lekatsas, Joerg Henkel, Srimat Chakradhar, Venkata Jakkula
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Publication number: 20060069857Abstract: A new compression and decompression architecture is herein disclosed which advantageously uses a plurality of parallel content addressable memories of different sizes to perform fast matching during compression.Type: ApplicationFiled: March 31, 2005Publication date: March 30, 2006Applicant: NEC Laboratories America, Inc.Inventors: Haris Lekatsas, Joerg Henkel, Venkata Jakkula, Srimat Chakradhar
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Publication number: 20060002555Abstract: An architecture for content-aware compression and/or encryption of various segments of a application is disclosed. The architecture advantageously allows decompression and decryption units to be placed various levels of a memory hierarchy.Type: ApplicationFiled: June 16, 2004Publication date: January 5, 2006Applicant: NEC Laboratories America, Inc.Inventors: Haris Lekatsas, Joerg Henkel, Srimat Chakradhar, Venkata Jakkula
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Publication number: 20060005047Abstract: A system architecture is disclosed that can support fast random access to encrypted memory.Type: ApplicationFiled: June 16, 2004Publication date: January 5, 2006Applicant: NEC Laboratories America, Inc.Inventors: Haris Lekatsas, Joerg Henkel, Srimat Chakradhar, Venkata Jakkula
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Patent number: 6892292Abstract: Code compression is known as an effective technique to reduce instruction memory size on an embedded system. However, code compression can also be very effective in increasing the processor-to-memory bandwidth and hence provide increased system performance. A code decompression engine having plurality of dictionary tables, coupled with decoding circuitry and appropriate control circuitry, is coupled between the processor core and the instruction cache. The code decompression engine provides one-cycle decompression of compressed instructions that are intermixed with uncompressed instructions, thereby increasing processor-to-memory bandwidth and avoiding processor stalls.Type: GrantFiled: May 1, 2002Date of Patent: May 10, 2005Assignee: NEC CorporationInventors: Joerg Henkel, Haris Lekatsas, Venkata Jakkula
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Publication number: 20040111710Abstract: A method for code compression of a program, the method comprising separating code from data. Software transformations necessary to make address mappings between compressed and uncompressed space are introduced into the code. Statistics are obtained about frequency of occurrence instructions, wherein said statistics include frequency of occurrence of two consecutive instructions. The program is parsed to identify occurrence of instructions or instruction pairs. The identified instructions are replaced with an address to a compressed bus-word table. An address mapping is generated from uncompressed address to compressed addresses.Type: ApplicationFiled: December 5, 2002Publication date: June 10, 2004Applicant: NEC USA, INC.Inventors: Srimat Chakradhar, Jorg Henkel, Venkata Jakkula, Haris Lekatsas, Murugan Sankaradass
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Patent number: 6741190Abstract: The power consumption of interconnects starts to have a significant impact on a system's total power consumption. Besides increasing buses (length, width) etc. this is mostly due to deep sub-micron effects where coupling capacitances between bus lines (wire-to-wire) are in the same order of magnitude as the base capacitances (wire-to-metal-layer). At that point, encoding schemes that solely address the minimization of transitions for the purpose of power reduction do not effectively work any more. Using a physical bus model that accurately models coupling capacitances, a signal bus encoding/decoding apparatus with encoding schemes that are partially adaptive and that take coupling effects into consideration is presented. The encoding schemes do not assume any a priori knowledge that is particular to a specific application.Type: GrantFiled: April 25, 2003Date of Patent: May 25, 2004Assignee: NEC CorporationInventors: Jörg Henkel, Haris Lekatsas
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Patent number: 6732256Abstract: A code compression method and apparatus for system-level power optimization that lessens the requirements imposed on main memory size. The apparatus utilizes a post-cache architecture that has a decompression engine that decompresses compressed object code instructions using dictionary look-up tables, branching instruction controllers and mathematical derivations based on bit toggling. The decompression engine extracts the compressed instructions from memory or the instruction/data cache using a bus compression technique to save power as the compressed instructions/data traverses the bus.Type: GrantFiled: June 17, 2003Date of Patent: May 4, 2004Assignees: NEC Corporation, Princeton UniversityInventors: Jörg Henkel, Wayne Wolf, Haris Lekatsas
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Patent number: 6691305Abstract: A code compression method for system-level power optimization that lessens the requirements imposed on main memory size. The method reduces the power consumption of a complete system comprising a CPU, instruction cache, data cache, main memory, data buses and address bus. The method includes extracting compressible instruction and data portions from executable code, creating a mathematical model of the extracted code portions, class the individual instructions in the extracted portions based upon their operation codes and compressing the instructions. The compressed instructions are further compressed when extracted from memory by using bus compaction. The method is also embodied in a computer system with a processor and a memory adapted to perform the steps of the method to compress the extracted instruction portions. Additionally, the method is embodied on a computer program product bearing software instructions adapted to perform the steps of the method to compress the extracted instruction portions.Type: GrantFiled: April 21, 2000Date of Patent: February 10, 2004Assignees: NEC Corporation, Princeton UniversityInventors: Jörg Henkel, Wayne Wolf, Haris Lekatsas
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Publication number: 20030212879Abstract: A code compression method for system-level power optimization that lessens the requirements imposed on main memory size. The method reduces the power consumption of a complete system comprising a CPU, instruction cache, data cache, main memory, data buses and address bus. The method includes extracting compressible instruction and data portions from executable code, creating a mathematical model of the extracted code portions, class the individual instructions in the extracted portions based upon their operation codes and compressing the instructions. The compressed instructions are further compressed when extracted from memory by using bus compaction. The method is also embodied in a computer system with a processor and a memory adapted to perform the steps of the method to compress the extracted instruction portions. Additionally, the method is embodied on a computer program product bearing software instructions adapted to perform the steps of the method to compress the extracted instruction portions.Type: ApplicationFiled: June 17, 2003Publication date: November 13, 2003Applicant: NEC CORPORATIONInventors: Jorg Henkel, Wayne Wolf, Haris Lekatsas
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Publication number: 20030201918Abstract: The power consumption of interconnects starts to have a significant impact on a system's total power consumption. Besides increasing buses (length, width) etc. this is mostly due to deep sub-micron effects where coupling capacitances between bus lines (wire-to-wire) are in the same order of magnitude as the base capacitances (wire-to-metal-layer). At that point, encoding schemes that solely address the minimization of transitions for the purpose of power reduction do not effectively work any more. Using a physical bus model that accurately models coupling capacitances, a signal bus encoding/decoding apparatus with encoding schemes that are partially adaptive and that take coupling effects into consideration is presented. The encoding schemes do not assume any a priori knowledge that is particular to a specific application.Type: ApplicationFiled: April 25, 2003Publication date: October 30, 2003Applicant: NEC CORPORATIONInventors: Jorg Henkel, Haris Lekatsas
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Publication number: 20030131216Abstract: Code compression is known as an effective technique to reduce instruction memory size on an embedded system. However, code compression can also be very effective in increasing the processor-to-memory bandwidth and hence provide increased system performance. A code decompression engine having plurality of dictionary tables, coupled with decoding circuitry and appropriate control circuitry, is coupled between the processor core and the instruction cache. The code decompression engine provides one-cycle decompression of compressed instructions that are intermixed with uncompressed instructions, thereby increasing processor-to-memory bandwidth and avoiding processor stalls.Type: ApplicationFiled: May 1, 2002Publication date: July 10, 2003Applicant: NEC USA, INC.Inventors: Joerg Henkel, Haris Lekatsas, Venkata Jakkula
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Patent number: 6583735Abstract: The power consumption of interconnects starts to have a significant impact on a system's total power consumption. Besides increasing buses (length, width) etc. this is mostly due to deep sub-micron effects where coupling capacitances between bus lines (wire-to-wire) are in the same order of magnitude as the base capacitances (wire-to-metal-layer). At that point, encoding schemes that solely address the minimization of transitions for the purpose of power reduction do not effectively work any more. Using a physical bus model that accurately models coupling capacitances, a signal bus encoding/decoding apparatus with encoding schemes that are partially adaptive and that take coupling effects into consideration is presented. The encoding schemes do not assume any a priori knowledge that is particular to a specific application.Type: GrantFiled: August 3, 2001Date of Patent: June 24, 2003Assignee: NEC CorporationInventors: Jörg Henkel, Haris Lekatsas
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Publication number: 20020186597Abstract: The power consumption of interconnects starts to have a significant impact on a system's total power consumption. Besides increasing buses (length, width) etc. this is mostly due to deep sub-micron effects where coupling capacitances between bus lines (wire-to-wire) are in the same order of magnitude as the base capacitances (wire-to-metal-layer). At that point, encoding schemes that solely address the minimization of transitions for the purpose of power reduction do not effectively work any more. Using a physical bus model that accurately models coupling capacitances, a signal bus encoding/decoding apparatus with encoding schemes that are partially adaptive and that take coupling effects into consideration is presented. The encoding schemes do not assume any a priori knowledge that is particular to a specific application.Type: ApplicationFiled: August 3, 2001Publication date: December 12, 2002Applicant: NEC USA, INC.Inventors: Jorg Henkel, Haris Lekatsas