Abstract: An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal. A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value.

Abstract: Methods and apparatus are provided for determining level-thresholds for q-level memory cells. A plurality of the memory cells are read to obtain respective read signal components. The read signal components are processed in dependence on signal level to produce a signal level vector, comprising a series of elements, indicative of the distribution of read signal components in order of signal level. The signal level vector is scanned with a sliding window of length greater than the spacing of successive window positions in the scan. At each window position, a metric Mi is calculated in dependence on the elements of the signal level vector in the window. A level-threshold for successive memory cell levels is then determined in dependence on variation of the metric over the scan.

Abstract: An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal. A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value.

Abstract: An apparatus for programming at least one multi-level Phase Change Memory (PCM) cell having a first terminal and a second terminal. A programmable control device controls the PCM cell to have a respective cell state by applying at least one current pulse to the PCM cell, the control device controlling the at least one current pulse by applying a respective first pulse to the first terminal and a respective second pulse applied to the second terminal of the PCM cell. The respective cell state is defined by a respective resistance level. The control device receives a reference resistance value defining a target resistance level for the cell, and further receives an actual resistance value of said PCM cell such that the applying the respective first pulse and said respective second pulse is based on said actual resistance value of the PCM cell and said received reference resistance value.

Abstract: A method is provided that comprises a step of programming the PCM cell to have a respective definite cell state by at least one current pulse flowing to the PCM cell, said respective definite cell state being defined at least by a respective definite resistance level, a step of controlling said respective current pulse by a respective bitline pulse and a respective wordline pulse, and a step of controlling said respective bitline pulse and said respective wordline pulse dependent on an actual resistance value of the PCM cell and a respective reference resistance value being defined for the definite resistance level.

Abstract: Methods and apparatus are provided for determining level-thresholds for q-level memory cells. A plurality of the memory cells are read to obtain respective read signal components. The read signal components are processed in dependence on signal level to produce a signal level vector, comprising a series of elements, indicative of the distribution of read signal components in order of signal level. The signal level vector is scanned with a sliding window of length greater than the spacing of successive window positions in the scan. At each window position, a metric Mi is calculated in dependence on the elements of the signal level vector in the window. A level-threshold for successive memory cell levels is then determined in dependence on variation of the metric over the scan.

Abstract: A method is provided that comprises a step of programming the PCM cell to have a respective definite cell state by at least one current pulse flowing to the PCM cell, said respective definite cell state being defined at least by a respective definite resistance level, a step of controlling said respective current pulse by a respective bitline pulse and a respective wordline pulse, and a step of controlling said respective bitline pulse and said respective wordline pulse dependent on an actual resistance value of the PCM cell and a respective reference resistance value being defined for the definite resistance level.

Abstract: A data storage device comprises a storage medium, at least one probe designed for creating indentation marks in the storage medium, a control unit designed for creating a control parameter (CTRL) acting on the probe resulting in the creation of one indentation mark. The control unit is further designed for modifying the control parameter (CTRL), if at least a given number of consecutive indentation marks with a given minimum distance between each other should be created. According to the method the control parameter (CTRL) is modified if at least a given number of consecutive marks with a given minimum distance between each other should be created.

Abstract: A method of operating a storage device includes storing data in the form of marks in a storage medium; scanning the storage medium with at least one probe operating in a scanning mode; and utilizing a control unit to provide a pulsed reading signal for data detecting in the scanning mode, and providing the probe with oversampling reading pulses in a clock mark scanning mode, wherein the control unit further comprises an input for a response signal to the oversampling reading pulses, and a determination unit for determining the clock dependent on the response signal; wherein the storage medium comprises marks for determining a clock of the pulsed reading signal.

Abstract: A data storage device comprises a storage medium, at least one probe designed for creating indentation marks in the storage medium, a control unit designed for creating a control parameter (CTRL) acting on the probe resulting in the creation of one indentation mark. The control unit is further designed for modifying the control parameter (CTRL), if at least a given number of consecutive indentation marks with a given minimum distance between each other should be created. According to the method the control parameter (CTRL) is modified if at least a given number of consecutive marks with a given minimum distance between each other should be created.

Abstract: A method and apparatus for overwriting data in a probe-based data storage device wherein data is represented by the presence and absence of pits formed in a storage surface by a probe of the device is provided. Input data is first coded such that successive bits of a given value x in the coded input data (b0, b1, b2, . . . ,) are separated by at least d bits of the complementary value {tilde over (x)}, where d is a predetermined number?2. Overwrite data bits (v0, v1, v2, . . . ,) are then generated by encoding the coded input data bits (b0, b1, b2, . . . ,).

Abstract: A method of operating a storage device includes storing data in the form of marks in a storage medium; scanning the storage medium with at least one probe operating in a scanning mode; and utilizing a control unit to provide a pulsed reading signal for data detecting in the scanning mode, and providing the probe with oversampling reading pulses in a clock mark scanning mode, wherein the control unit further comprises an input for a response signal to the oversampling reading pulses, and a determination unit for determining the clock dependent on the response signal; wherein the storage medium comprises marks for determining a clock of the pulsed reading signal.

Abstract: A method and apparatus for overwriting data in a probe-based data storage device wherein data is represented by the presence and absence of pits formed in a storage surface by a probe of the device is provided. Input data is first coded such that successive bits of a given value x in the coded input data (b0, b1, b2, . . . ,) are separated by at least d bits of the complementary value x, where d is a predetermined number?2. Overwrite data bits (v0, v1, v2, . . . ,) are then generated by encoding the coded input data bits (b0, b1, b2, . . . ,).

Abstract: A storage device and a method for operating a storage device. A storage medium for storing data in form of marks is scanned by at least one probe in a scanning mode. A control unit provides a pulsed reading signal for data detecting purposes in said scanning mode. Said storage medium comprises marks for determining a clock of said pulsed signal.