Patents by Inventor Harish Gajula

Harish Gajula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11960758
    Abstract: Rather than use one long folding operation to fold data from single-level cell (SLC) blocks into a multi-level cell (MLC) block, a storage system uses a multi-stage folding operation. By breaking up the folding process into stages, SLC blocks involved in an earlier stage can be released prior to a subsequent stage being performed. This can increase performance of the storage system by releasing SLC source blocks sooner and reducing an SLC block budget requirement.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: April 16, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Bhanushankar Doni Gurudath, Harish Gajula
  • Publication number: 20240021249
    Abstract: Technology is disclosed herein for multi-stage data compaction. In a first data compaction stage valid data fragments from source erase block(s) are programmed into a destination erase block at two bits per memory cell. In a second data compaction stage additional valid data from the source erase block(s) is programmed into the destination erase block at two bits per memory cell. In this second stage, the same physical pages of memory cells in the destination erase block may be programmed such that each memory cell in the destination erase block is programmed to four bits.
    Type: Application
    Filed: July 14, 2022
    Publication date: January 18, 2024
    Applicant: Western Digital Technologies, Inc.
    Inventors: Harish Gajula, Bhanushankar Doni
  • Publication number: 20230325105
    Abstract: Rather than use one long folding operation to fold data from single-level cell (SLC) blocks into a multi-level cell (MLC) block, a storage system uses a multi-stage folding operation. By breaking up the folding process into stages, SLC blocks involved in an earlier stage can be released prior to a subsequent stage being performed. This can increase performance of the storage system by releasing SLC source blocks sooner and reducing an SLC block budget requirement.
    Type: Application
    Filed: April 6, 2022
    Publication date: October 12, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Bhanushankar Doni Gurudath, Harish Gajula