Patents by Inventor Harish Ganapathy
Harish Ganapathy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230369509Abstract: Techniques are provided herein for forming thin film transistor (TFT) structures having one or more doped contact regions. The addition of certain dopants can be used to increase conductivity and provide higher thermal stability in the contact regions of the TFT. Memory structures having TFT structures are arranged in a two-dimensional array within one or more interconnect layers and stacked in a vertical direction such that multiple tiers of memory structure arrays are formed within the interconnect region. Any of the TFT structures within the memory structures may include one or more contacts that are doped with additional elements. The doping profile of the contacts can be tuned to optimize performance, stability, and reliability of the TFT structure. Furthermore, additional doping may be performed within the area beneath the contacts and extending into the semiconductor region.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Applicant: Intel CorporationInventors: Jisoo Kim, Xiaoye Qin, Timothy Jen, Harish Ganapathy, Van H. Le, Huiying Liu, Prem Chanani, Cheng Tan, Shailesh Kumar Madisetti, Abhishek Anil Sharma, Brian Wadsworth, Vishak Venkatraman, Andre Baran
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Publication number: 20230369340Abstract: Techniques are provided herein for forming thin film transistor structures having co-doped semiconductor regions. The addition of insulating dopants can be used to improve the performance, stability, and reliability of the TFT. A given TFT structure within an array of similar TFT structures formed in an interconnect region may include a semiconductor region that is co-doped with one or more additional elements. The doping profile can be tuned to optimize performance, stability, and reliability of the TFT structure. In some embodiments, the doping profile causes an overall reduction in the conductivity of the semiconductor region, leading to a higher threshold voltage. Designing access devices (in, for example, a DRAM architecture) with higher threshold voltages can be beneficial for improving reliability of the memory cell.Type: ApplicationFiled: May 12, 2022Publication date: November 16, 2023Applicant: Intel CorporationInventors: Van H. Le, Timothy Jen, Vishak Venkatraman, Shailesh Kumar Madisetti, Cheng Tan, Harish Ganapathy, James Pellegren, Kamal H. Baloch, Abhishek Anil Sharma
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Patent number: 11784088Abstract: Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.Type: GrantFiled: January 29, 2019Date of Patent: October 10, 2023Assignee: Intel CorporationInventors: Chieh-Jen Ku, Bernhard Sell, Pei-Hua Wang, Harish Ganapathy, Leonard C. Pipes
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Publication number: 20230307291Abstract: An integrated circuit includes a first layer comprising dielectric material. One or both of an interconnect feature and a device are within the dielectric material of the first layer. The integrated circuit further includes a second layer above the first layer, where the second layer includes dielectric material. A third layer is between the first layer and the second layer. In an example, the third layer can be, for example, an etch stop layer or a liner layer or barrier layer. In an example, an impurity is within the first layer and the third layer. In an example, the impurity has a detectable implant depth profile such that a first distribution of the impurity is within the first layer and a second distribution of the impurity is within the third layer.Type: ApplicationFiled: March 24, 2022Publication date: September 28, 2023Applicant: Intel CorporationInventors: Moshe Dolejsi, Harish Ganapathy, Travis W. Lajoie, Deepyanti Taneja, Huiying Liu, Cheng Tan, Timothy Jen, Van H. Le, Abhishek A. Sharma
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Publication number: 20220359758Abstract: Transistors with metal oxide channel material and a multi-composition gate dielectric. A surface of a metal oxide gate dielectric may be nitrided before deposition of a metal oxide channel material, for example to reduce gate capacitance of a TFT. Breakdown voltage and/or drive current of a TFT can be increased through the introduction of an additional metal oxide and/or nitride between the gate electrode and a metal oxide gate dielectric. The introduction of an intervening layer between two layers of a metal oxide gate dielectric can also increase breakdown voltage and/or drive current of a TFT.Type: ApplicationFiled: May 5, 2021Publication date: November 10, 2022Applicant: Intel CorporationInventors: Shailesh Kumar Madisetti, Chieh-Jen Ku, Wen-Chiang Hong, Pei-Hua Wang, Cheng Tan, Harish Ganapathy, Bernhard Sell, Lin-Yung Wang
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Publication number: 20200243376Abstract: Embodiments disclosed herein include transistors and methods of forming such transistors. In an embodiment, the transistor may comprise a semiconductor channel with a first surface and a second surface opposite the first surface. In an embodiment, a source electrode may contact the first surface of the semiconductor channel and a drain electrode may contact the first surface of the semiconductor channel. In an embodiment, a gate dielectric may be over the second surface of the semiconductor channel and a gate electrode may be separated from the semiconductor channel by the gate dielectric. In an embodiment, an isolation trench may be adjacent to the semiconductor channel. In an embodiment, the isolation trench comprises a spacer lining the surface of the isolation trench, and an isolation fill material.Type: ApplicationFiled: January 29, 2019Publication date: July 30, 2020Inventors: Chieh-Jen KU, Bernhard SELL, Pei-Hua WANG, Harish GANAPATHY, Leonard C. PIPES
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Publication number: 20200189046Abstract: A locomotive heat exchanger apparatus includes a header having at least one opening, at least one tubular member joined to the header and having an interior passageway in fluid communication with the at least one opening, and a plurality of radial fins extending from the at least one tubular member. The tubular member and the plurality of radial fins may be formed as a unitary component via additive manufacturing without welding or interference fit.Type: ApplicationFiled: December 12, 2018Publication date: June 18, 2020Applicant: GENERAL ELECTRIC COMPANYInventors: BALAJI HOSADURGAM RAVINDRANATH, HARISH GANAPATHY
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Patent number: 9008710Abstract: Methods, apparatuses, and computer program products for controlling communication between whitespace devices are provided.Type: GrantFiled: June 14, 2012Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Malolan Chetlur, Harish Ganapathy, Shivkumar Kalyanaraman, Mukundan Madhavan
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Publication number: 20130172032Abstract: Methods, apparatuses, and computer program products for controlling communication between whitespace devices are provided.Type: ApplicationFiled: December 29, 2011Publication date: July 4, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Malolan Chetlur, Harish Ganapathy, Shivkumar Kalyanaraman, Mukundan Madhavan
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Publication number: 20130172033Abstract: Methods, apparatuses, and computer program products for controlling communication between whitespace devices are provided.Type: ApplicationFiled: June 14, 2012Publication date: July 4, 2013Applicant: International Business Machines CorporationInventors: Malolan Chetlur, Harish Ganapathy, Shivkumar Kalyanaraman, Mukundan Madhavan