Abstract: A method for accurately and efficiently simulating power behavior of digital VLSI MOS circuit at the gate-level. The method characterizes both the static and dynamic power consumed by a cell for different logic state conditions on all its ports. For each state-vector, power-consumption measurements are carried out for different conditions of input ramp and output load. The method looks at the power behavior of each state-vector for different values of input ramp and output loads as allowed by the technology of that cell. The exhibited power behavior is then modeled in terms of power-coefficients of the power dissipation model. These power-coefficients, which are determined by the characterizer, provide a mechanism to capture the different power consumption dependencies under varying state-vector conditions, input ramp, and output load for different types of cells. The model is unique as it has the same form for all cells, but its coefficients are customizable for each power vs. input-ramp vs.

Abstract: A power usage simulator and method for generating a baseline power usage model for a representative sample of cells in a circuit cell library, where the baseline power model is based on signal slew rates and output load for a given of environmental conditions. The baseline power usage model is aggregated for a representative set of library cells so as to provide an accurate baseline power usage computation for all logic cells rather than for each transistor or each individual cell. Thereafter, power coefficient sensitivities to varying temperature, supply voltage and process conditions are determined for each power coefficient. Power coefficient sensitivities are measured by comparing the ratios of the measured power coefficients resulting from maintaining two of the three parameters (temperature, voltage and process) at baseline values while varying the third parameter over its entire range.

Abstract: A power usage simulator generates, for all the logic cells in a circuit cell library, a power model that characterizes a cell's power consumption behavior as a two-part, piecewise-linear function based on signal slew rates and output load. A logic simulator is modified so that for each signal transition in a specified logic circuit, the logic simulator performs a power usage computation utilizing the power usage model for all cells affected by each signal transition. The power usage value for each signal transition is posted to a power usage output data structure, with each posted power usage value having an associated time value. The posted power usage values are then analyzed by (A) accumulating the posted power usage values to provide a total power usage value, and (B) clocking the accumulation of power usage values with an end user set clock rate so as to produce a power usage profile indicating the time varying rate of power consumption during the simulation time period.