Abstract: Circuits for low noise amplifiers with interferer reflecting loops are provided. In some embodiments, circuits for a low noise amplifier with an interferer reflecting loop are provided, the circuits comprising: a low noise amplifier (LNA) having an input and an output; a buffer having an input coupled to the output of the LNA and an output; and notch filter having an input coupled to the output of the buffer and an output coupled to the input of the LNA.

Abstract: A plurality of receivers each having: an RF amplifier having an RFAMP input coupled to an antenna and having an RFAMP output; a capacitor having a CAP first side connected to the RFAMP output and a CAP second side; a passive mixer coupled to the RFAMP input, the CAP second side, and the output of a local oscillator phase shifter; an operational transconductor amplifier having an OTA input connected to the CAP second side and having an OTA output; a feedback resistor connected between the OTA input and the OTA output; a baseband transconductor having a BBGM input connected to the OTA input and a BBGM output; a cancelling transconductor having a CANCELLER output connected to the BBGM output and having a CANCELLER input; and an attenuator between the OTA output and the CANCELLER input, wherein the OTA output of each of the plurality of receivers are connected together.

Abstract: Full duplex transceivers are provided, the transceivers comprising: a transmitter section that includes an analog portion having analog baseband signals and a digital portion having digital baseband signals; a receiver section that includes an analog portion having analog baseband signals and a digital portion having digital baseband signals; an analog self-interference canceller that, in response to the analog baseband signals in the analog portion of the transmitter section, produces analog cancellation signals that cancel first self-interference in the analog baseband signals in the analog portion of the receiver section; and a digital self-interference canceller that, in response to the digital baseband signals in the digital portion of the transmitter section, produces digital cancellation signals that cancel second self-interference in the digital baseband signals in the digital portion of the receiver section.

Abstract: Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M1 having gate coupled to input signal and first bias voltage BV1 and source coupled to the drains of the BWSTs; transistor M2 having gate coupled to BV2 and source coupled to the drain of M1; transistor M3 having gate coupled to BV3 and source coupled to the drain of M2; transistor having gate coupled to BV4, source coupled to the drain of M3; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M4.

Abstract: Self-interference cancellers are provided. The self-interference cancellers can include multiple second-order, N-path Gm-C filters. Each filter can be configured to cancel self-interference on a channel of a desired bandwidth. Each filter can be independently controlled using a variable transmitter resistance, a variable receiver resistance, a variable baseband capacitance, a variable transconductance, and a variable time shift between local oscillators that control switches in the filter. By controlling these variables, magnitude, phase, slope of magnitude, and slope of phase of the cancellers frequency responses can be controlled for self-interference cancellation. A calibration process is also provided for configuring the canceller.

Abstract: A plurality of receivers each having: an RF amplifier having an RFAMP input coupled to an antenna and having an RFAMP output; a capacitor having a CAP first side connected to the RFAMP output and a CAP second side; a passive mixer coupled to the RFAMP input, the CAP second side, and the output of a local oscillator phase shifter; an operational transconductor amplifier having an OTA input connected to the CAP second side and having an OTA output; a feedback resistor connected between the OTA input and the OTA output; a baseband transconductor having a BBGM input connected to the OTA input and a BBGM output; a cancelling transconductor having a CANCELLER output connected to the BBGM output and having a CANCELLER input; and an attenuator between the OTA output and the CANCELLER input, wherein the OTA output of each of the plurality of receivers are connected together.

Abstract: In some embodiments, circuits for providing Class-E power amplifiers are provided, the circuits comprising: a first switch having a first side and a second side; a first Class-E load network coupled to the first side of the first switch; a second Class-E load network; and a second switch having a first side and a second side, the first side of the second switch being coupled the second side of the first switch and the second Class-E load network. In some embodiments, the circuits further comprise: a third switch having a first side and a second side; a third Class-E load network coupled to the first side of the third switch; a fourth Class-E load network; and a fourth switch having a first side and a second side, the first side of the fourth switch being coupled the second side of the third switch and the fourth Class-E load network.

Abstract: Full duplex transceivers are provided, the transceivers comprising: a transmitter section that includes an analog portion having analog baseband signals and a digital portion having digital baseband signals; a receiver section that includes an analog portion having analog baseband signals and a digital portion having digital baseband signals; an analog self-interference canceller that, in response to the analog baseband signals in the analog portion of the transmitter section, produces analog cancellation signals that cancel first self-interference in the analog baseband signals in the analog portion of the receiver section; and a digital self-interference canceller that, in response to the digital baseband signals in the digital portion of the transmitter section, produces digital cancellation signals that cancel second self-interference in the digital baseband signals in the digital portion of the receiver section.

Abstract: Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M1 having gate coupled to input signal and first bias voltage BV1 and source coupled to the drains of the BWSTs; transistor M2 having gate coupled to BV2 and source coupled to the drain of M1; transistor M3 having gate coupled to BV3 and source coupled to the drain of M2; transistor having gate coupled to BV4, source coupled to the drain of M3; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M4.

Abstract: Circuits and methods for antenna-based self-interference cancellation are provided. In some embodiments, circuits for antenna-based self-interference cancellation are provided, the circuits comprising: a transmit antenna having a transmit port that receives a transmit signal; a receive antenna having a receive port that is cross-polarized with respect to the transmit port and having an auxiliary port that is co-polarized with respect to the transmit port; and a termination connected to the auxiliary port that reflects a signal received at the auxiliary port as a reflected signal, wherein the reflected signal counters interference caused by the transmit signal at the receive port.

Abstract: Circuits for power-combined power amplifier array are provided, the circuits comprising: an input splitter coupled to an input that provides a plurality of outputs; a plurality of power amplifier unit cells, each power amplifier unit cell coupled to a corresponding output of the input splitter and each power amplifier unit cell providing an output signal at an output of the power amplifier unit cell; and a power combiner having an output, a plurality of inputs, each input coupled to the output of a corresponding power amplifier unit cell, and a plurality of C-L-C-section equivalents, each having an input connected to a corresponding one of the plurality of inputs of the power combiner and an output connected to the output of the power combiner.

Abstract: Circuits for reducing out-of-band-modulated transmitter self-interference are provided. In some embodiments, receivers are provided, the receivers comprising: a low noise amplifier (LNA) having an input, a first output, and a second output, wherein the LNA includes: a common source transistor having a gate coupled to an input signal, a drain coupled to the first output of the LNA, and a source coupled to ground; and a common gate transistor having a gate coupled to a transmitter replica signal, a source coupled to the gate of the common source transistor, and a drain coupled to the second output of the LNA.

Abstract: Circuits for low noise amplifiers with interferer reflecting loops are provided. In some embodiments, circuits for a low noise amplifier with an interferer reflecting loop are provided, the circuits comprising: a low noise amplifier (LNA) having an input and an output; a buffer having an input coupled to the output of the LNA and an output; and notch filter having an input coupled to the output of the buffer and an output coupled to the input of the LNA.

Abstract: Circuits and methods for performing harmonic rejection mixing are provided. In some embodiments, the circuit comprises: a first amplifier that amplifies a received signal at a first gain; a second amplifier that amplifies the received signal at a fraction of the first gain; a mixer that receives a local oscillator signal having a first fundamental frequency and the first amplifier output, and outputs a first mixed signal; a second mixer that receives a second local oscillator signal having a fundamental frequency that is a multiple of the first fundamental frequency and the second amplifier output, and outputs a second mixed signal; and an output stage that receives the first and second mixed signals and outputs a sum of the first and second mixed signals.

Abstract: In some embodiments, circuits for providing Class-E power amplifiers are provided, the circuits comprising: a first switch having a first side and a second side; a first Class-E load network coupled to the first side of the first switch; a second Class-E load network: and a second switch having a first side and a second side, the first side of the second switch being coupled the second side of the first switch and the second Class-E load network. In some embodiments, the circuits further comprise: a third switch having a first side and a second side; a third Class-E load network coupled to the first side of the third switch; a fourth Class-E load network; and a fourth switch having a first side and a second side, the first side of the fourth switch being coupled the second side of the third switch and the fourth Class-E load network.

Abstract: Circuits comprising: digital-to-amplitude converter (DAC), comprising: binary weighted switching transistors (BWSTs), each having gate coupled to amplitude control bit ACB, and wherein the drain of each of the BWSTs are connected together and wherein the source of each of the BWSTs are connected together; transistor M1 having gate coupled to input signal and first bias voltage BV1 and source coupled to the drains of the BWSTs; transistor M2 having gate coupled to BV2 and source coupled to the drain of M1; transistor M3 having gate coupled to BV3 and source coupled to the drain of M2; transistor having gate coupled to BV4, source coupled to the drain of M3; and inverter having input coupled to another ACB and having output coupled to the output of the DAC and the drain of M4.

Abstract: Circuits and methods for performing harmonic rejection mixing are provided. In some embodiments, the circuit comprises: a first amplifier that amplifies a received signal at a first gain; a second amplifier that amplifies the received signal at a fraction of the first gain; a mixer that receives a local oscillator signal having a first fundamental frequency and the first amplifier output, and outputs a first mixed signal; a second mixer that receives a second local oscillator signal having a fundamental frequency that is a multiple of the first fundamental frequency and the second amplifier output, and outputs a second mixed signal; and an output stage that receives the first and second mixed signals and outputs a sum of the first and second mixed signals.

Abstract: In some embodiments, circuits for providing Class-E power amplifiers are provided, the circuits comprising: a first switch having a first side and a second side; a first Class-E load network coupled to the first side of the first switch; a second Class-E load network: and a second switch having a first side and a second side, the first side of the second switch being coupled the second side of the first switch and the second Class-E load network. In some embodiments, the circuits further comprise: a third switch having a first side and a second side; a third Class-E load network coupled to the first side of the third switch; a fourth Class-E load network; and a fourth switch having a first side and a second side, the first side of the fourth switch being coupled the second side of the third switch and the fourth Class-E load network.

Abstract: A method and system for tracking quality of life in a patient with angina includes obtaining activity data and cardiac data, determining a level of physical activity of the patient and identifying an ischemic episode based on the cardiac data obtained during the physical activity. The method also provides for recording an activity level at the time the ischemic episode occurs. Furthermore, the method also provides for presenting activity level trends related to activity levels at the onset of ischemia to a user.

Abstract: Cardiac activity is sensed over a plurality of heart beats defining a beat set. For each beat in the set, it is determined whether the beat is a non-classified beat (e.g., paced beat, a beat outside of a specified heart rate range or a PVC), or a classified beat. For each classified beat, it is determined whether the beat is a non-detect beat, a minor beat or a major beat. Counts of classified beats, non-classified beats, major beats, minor beats, and non-detect beats are maintained. The beat set is declared to be one of a non-classified set, a major set, a minor set or a non-detect set based on the relative counts of classified beats, non-classified beats, major beats, minor beats, and non-detect beats. Over a period of time, counts of beat-set types are maintained and entry into and exit from ST episodes are determined based on these beat-set counts.