Abstract: Disclosed subject matter relates to verification and debugging tool and method for providing Register Transfer Level (RTL) code block storage and analysis. Verification and debugging tool includes input interface configured to receive RTL code in Hardware Description Language (HDL). Further, verification and debugging tool includes RTL parser configured to parse RTL code, and generate abstract syntax tree representing syntactic structure of RTL code. Thereafter, verification and debugging tool includes graph converter adapted to convert abstract syntax tree into RTL directed graph. Furthermore, verification and debugging tool includes memory configured to store node block structures. Each node block structure includes at least one of pointers to fan-in nodes, fanout nodes and one or more custom fields indicating behavior description of node. Finally, verification and debugging tool includes visual display configured to display RTL directed graph.

Abstract: Disclosed subject matter relates to verification and debugging tool and method for providing sensitive regions around and in Register Transfer Level (RTL) code objects. The verification and debugging tool includes input interface configured to receive RTL code in Hardware Description Language (HDL). Further, verification and debugging tool includes RTL parser configured to parse RTL code, and generate abstract syntax tree representing syntactic structure of RTL code. Thereafter, verification and debugging tool includes graph converter configured to convert abstract syntax tree into RTL directed graph. Furthermore, verification and debugging tool includes visual display configured to display code blocks, each exhibiting sensitive regions. Finally, verification and debugging tool includes objects extractor configured to detect user actions related to sensitive regions.

Abstract: Disclosed subject matter relates to verification and debugging tool and method for providing spatial display of Register Transfer Level (RTL) code on a visual display. The verification and debugging tool includes an input interface configured to receive RTL code in a Hardware Description Language (HDL). Further, the verification and debugging tool includes an RTL parser configured to parse the RTL code, and generate an abstract syntax tree representing the syntactic structure of the RTL code. Thereafter, the verification and debugging tool includes a graph converter adapted to convert the abstract syntax tree into an RTL directed graph. Finally, the verification and debugging tool includes a visual display configured to display the RTL directed graph. The visual display simultaneously allows visualization of multiple code blocks and corresponding interconnections.

Abstract: A circuit includes an anisotropic magnetoresistance (AMR) sensor; an operational amplifier; and a calibration circuit. The AMR sensor has a first terminal, a second terminal, a third terminal, and a fourth terminal. The operational amplifier has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the operational amplifier is coupled to the second terminal of the AMR sensor. The second terminal of the operational amplifier is coupled to the third terminal of the AMR sensor. The calibration circuit is coupled to the first terminal of the operational amplifier. The calibration circuit is configured to provide an adjustable offset trim voltage at the first terminal of the operational amplifier to cancel out an offset voltage generated by the AMR sensor.

Abstract: In various examples, a region including at least two vector objects that can be intertwined is determined. For example, vector objects can be intertwined by at least determining a set of outlines for the vector objects and detecting regions within which the vector objects overlap. In such examples, a visual order of the vector objects is determined based on an input from a user.

Abstract: Digital representation techniques of intertwined vector objects are described. These techniques support a non-destructive representation of intertwined digital objects. Additionally, these techniques support editing of overlaps to change a visual ordering in an intuitive and efficient manner. Optimization operations are also implemented that remove redundancy, combine overlaps into a single representation, address visual artifacts at borders between the intertwined objected, and so forth.

Abstract: A method including receiving a first position of a sun visor of a vehicle; receiving a route of the vehicle from a navigation system of the vehicle, the route having at least one waypoint; determining a predicted amount of sunlight in an occupant's eyes at the at least one waypoint of the route; determining whether the predicted amount of sunlight in the occupant's eyes at the at least one waypoint of the route is greater than a predefined threshold amount; and instructing the sun visor to move to a second position in response to the predicted amount of sunlight exceeding the predefined threshold amount to block at least a portion of the predicted amount of sunlight from the occupant's eyes at the at least one waypoint is disclosed.

Abstract: Methods, systems, and non-transitory computer readable storage media are disclosed for generating segmentations of a raster image via a half-edge mesh structure with scanline operations. The disclosed system determines, during scanline operations on a raster image, a plurality of sets of adjacent pixels having a common color value in the raster image. The disclosed system determines, during the scanline operations on the raster image, a plurality of half-edges at edges of pixels along a boundary of a set of adjacent pixels of the plurality of sets of adjacent pixels with next half-edge directions indicating directions of subsequent half-edges along the boundary of the set of adjacent pixels. The disclosed system generates one or more oriented polyline boundary loops representing the boundary of the set of adjacent pixels from the plurality of half-edges and the next half-edge directions of the set of adjacent pixels.

Abstract: A scan reset control circuit includes a single scan reset input configured to receive a reset signal, a plurality of scan reset outputs configured to be coupled to a plurality of circuit blocks in a one-to-one ratio, a plurality of writable non-scan test data registers including register outputs configured to assert or deassert the reset signal, and a plurality of reset enable circuits coupled to the plurality of scan reset outputs in a one-to-one ratio. Each of the scan reset outputs is configured to simultaneously reset a set of scan flip-flops of the corresponding circuit block. Each of the plurality of reset enable circuits includes an input coupled to the single scan reset input, a selector input coupled to the register outputs, and an output coupled to the corresponding scan reset output.

Abstract: A scan reset control circuit includes a single scan reset input configured to receive a reset signal, a plurality of scan reset outputs configured to be coupled to a plurality of circuit blocks in a one-to-one ratio, a plurality of writable non-scan test data registers including register outputs configured to assert or deassert the reset signal, and a plurality of reset enable circuits coupled to the plurality of scan reset outputs in a one-to-one ratio. Each of the scan reset outputs is configured to simultaneously reset a set of scan flip-flops of the corresponding circuit block. Each of the plurality of reset enable circuits includes an input coupled to the single scan reset input, a selector input coupled to the register outputs, and an output coupled to the corresponding scan reset output.

Abstract: The present disclosure is directed toward systems, methods, and non-transitory computer readable media that provide assistive guides for path tracing of raster images. In particular, in one or more implementations, the disclosed systems determine a set of outlines corresponding to boundaries of a set of segments within a raster image. The disclosed systems select, from the set of outlines, an outline corresponding to a segment in response to a client device input indicating point(s) located within a threshold distance of the outline. The disclosed systems provide, for display within a graphical user interface of a client device, a highlighted indication of the outline corresponding to the segment. The disclosed systems generate, within a vector image, a vector path based on the outline corresponding to the segment in response to a selection of the outline via the graphical user interface.

Abstract: The present disclosure relates to systems, methods, and non-transitory computer-readable media that generates a modified digital image with a modified rendering order of objects within a digital image. For instance, the disclosed systems generate, in response to an input indicating a selected region of a digital image, an object mask for a first object located at least partially within the selected region of the digital image and further generate a vectorized object mask including a boundary of the first object from the object mask. The disclosed systems determine an overlapping region of the vectorized object mask with the selected region and an additional vectorized object mask. The disclosed systems generate a modified digital image by modifying a rendering order of a portion of the first object corresponding to the selected region and a portion of a second object overlapping the portion of the first object within the selected region.

Abstract: The present disclosure relates to systems, non-transitory computer-readable media, and methods for generating intertwined digital designs according to the visual order of structural graph nodes. In particular, in one or more embodiments, the disclosed systems generate, by at least one processor, a structural graph of a digital design that represents overlapping surfaces of objects in the digital design as nodes and object paths between the overlapping surfaces as edges. Further, the disclosed systems assign, by the at least one processor, a visual order to the nodes based on a configuration of the structural graph. Moreover, the disclosed systems generate, by the at least one processor, an intertwined digital design by ordering the overlapping surfaces of the objects in accordance with the assigned visual order of the nodes.

Abstract: In implementations of systems for visual reordering of partial vector objects, a computing device implements an order system to receive input data describing a region specified relative to a group of vector objects that includes a portion of a first vector object and a portion of second vector object. A visual order as between the portion of the first vector object and the portion of the second vector object within the region is determined. The order system computes a modified visual order as between the portion of the first vector object and the portion of the second vector object within the region based on the visual order. The order system generates the group of vector objects for display in a user interface using a render surface and a sentinel value to render pixels within the region in the modified visual order.

Abstract: A method includes generating a reference voltage by periodically switching direction of current flow in a diagnostic sensor, where the reference voltage is a non-sinusoidal differential voltage of which an amplitude alternates between minimum and maximum values, and where the reference voltage includes a diagnostic sensor output voltage component responsive to an external magnetic field and a diagnostic sensor offset voltage component responsive to a mismatch of the diagnostic sensor. The method also includes amplifying the reference voltage to produce an amplified reference voltage, where the amplified reference voltage is a differential voltage having an amplifier offset voltage component. Additionally, the method includes demodulating the amplified reference voltage by filtering the diagnostic sensor offset voltage component and the amplifier offset voltage component to produce a demodulated voltage. Also, the method includes digitizing the demodulated voltage to produce a digitized voltage.

Abstract: Digital representation techniques of intertwined vector objects are described. These techniques support a non-destructive representation of intertwined digital objects. Additionally, these techniques support editing of overlaps to change a visual ordering in an intuitive and efficient manner. Optimization operations are also implemented that remove redundancy, combine overlaps into a single representation, address visual artifacts at borders between the intertwined objected, and so forth.

Abstract: A circuit includes an anisotropic magnetoresistance (AMR) sensor; an operational amplifier; and a calibration circuit. The AMR sensor has a first terminal, a second terminal, a third terminal, and a fourth terminal. The operational amplifier has a first terminal, a second terminal, a third terminal, and a fourth terminal. The first terminal of the operational amplifier is coupled to the second terminal of the AMR sensor. The second terminal of the operational amplifier is coupled to the third terminal of the AMR sensor. The calibration circuit is coupled to the first terminal of the operational amplifier. The calibration circuit is configured to provide an adjustable offset trim voltage at the first terminal of the operational amplifier to cancel out an offset voltage generated by the AMR sensor.

Abstract: Embodiments are disclosed for interlacing vector objects. A method of interlacing vector objects may include receiving a selection of a first vector object of an image. The method may further include detecting a second vector object of the image, wherein the second vector object is different than the first vector object. The method may further include determining a first depth position for the first vector object and a second depth position for the second vector object. The method may further include interlacing the second vector object and the first vector object, wherein interlacing comprises drawing the first vector object based on the first depth position and the second vector object based on the second depth position.

Abstract: In various examples, a region including at least two vector objects that can be intertwined is determined. For example, vector objects can be intertwined by at least determining a set of outlines for the vector objects and detecting regions within which the vector objects overlap. In such examples, a visual order of the vector objects is determined based on an input from a user.

Abstract: Graphics processing unit instancing control techniques are described that overcome conventional challenges to expand functionality made available via a graphics processing unit. In one example, these techniques support ordering of primitives within respective instances of a single draw call made to a graphics processing unit. This is performed by ordering primitives within respective instances that correspond to polygons for rendering. The ordering of the primitives overcomes limitations of conventional techniques and reduces visual artifacts through support of correct overlaps and z-ordering of instances.