Abstract: It is described an attenuation measurement device (100), comprising: i) a detector unit (110) having a coupling capacitance (120), and an input capacitance (130), wherein the detector unit (110) is configured to produce a detector output signal (112a,b) in reply to an input signal received at the coupling capacitance (120) and/or at the input capacitance (130); ii) a test unit (140), coupled to the detector unit (110), and configured to provide a test signal (141) with at least one known signal property as a first input signal to the coupling capacitance (120); iii) a calibration unit (150), coupled to the detector unit (110), and configured to provide a calibration signal (151) as a second input signal to the input capacitance (130); and iv) a control unit configured to a) determine a first detector output signal (112a) produced by the detector unit (110) in response to the test signal (141), b) identify a specific calibration signal (151) that yields a second detector output signal (112b) that is compa

Abstract: Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a second degeneration resistor is coupled between a source of the first N-channel transistor and a second supply voltage. A first low impedance bypass circuit is coupled between the sources of the first P-channel transistor and the first N-channel transistor.

Abstract: Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a second degeneration resistor is coupled between a source of the first N-channel transistor and a second supply voltage. A first low impedance bypass circuit is coupled between the sources of the first P-channel transistor and the first N-channel transistor.

Abstract: A communication apparatus (200) has a calibration mode in which a signal is passed through circuitry (30, 80) of the apparatus, and a controller (160) measures the response of the circuitry (30, 80) to the signal and adjusts the circuitry (30, 80) to improve performance. The signal used for calibration has a wider bandwidth than the bandwidth of signals used for transmission. The wider bandwidth may be provided by reconfiguring a digital filter (20) from low-pass to high-pass.

Abstract: A frequency hopping receiver circuit has a frequency converter (12) and a hopping control circuit (14) coupled to the frequency converter (12), and configured to control frequency hopping of the received frequency, by controlling changes in frequency shift applied by the frequency converter (12). The frequency change is applied in combination with a temporary reduction in conversion gain of the frequency converter (12) during the change in frequency shift. The frequency converter may contain a mixer (122), a local oscillator circuit (120) and a controllable amplifier (124) coupled between the input of the frequency converter (12) and the mixer (122) or between the mixer (122) and the output of the frequency converter (12), or between the local oscillator circuit (120) and the local oscillator input of the mixer (122).

Abstract: A power supply arrangement is for supplying power to a chip core. A dc-dc converter arrangement is used both for a wake-up state of the core in preparation for an active state, and for a shut down charge recycling state in which the core supplies charge to the dc-dc converter. Thus, the dc-dc converter arrangement functions both to control powering on of the core in an efficient manner and the powering down of the core to implement charge recycling. In an active state, the core is supplied with power from the high power supply line.

Abstract: Data is received with a transceiver circuit with a receiver branch (14) that comprises a notch filter (140) and a digital Fourier transformer (146). Furthermore the transceiver circuit has a transmitter branch (16) comprising an inverse digital Fourier transformer (160). Prior to reception the transceiver circuit is switched to a calibration mode, wherein an output of the transmitter branch (16) is coupled to an input of the notch filter (140). The inverse digital Fourier transformer (160) of the transmitter is used to compute an inverse transform of a spectrum with a frequency component at a selected position. A signal derived from the inverse transform is applied to an input of the notch filter (140) in the calibration mode. The digital Fourier transformer (146) is used to Fourier transform an output signal of the notch filter (140). A control setting of the notch filter to suppress the frequency component from an output of the digital Fourier transformer (146) is determined.

Abstract: Pulses are detected in a communications receiver by programming each of a plurality of comparators (44a, 44b, . . . , 44n) with a sampling time point selected from a plurality of sampling time points (58, 60) and with a reference level selected from a plurality of reference levels (54, 56). The received signal is applied to each of the comparators such that each of the comparators produces a respective output signal based on a comparison between the received signal level and the selected reference level at the selected sampling time point. The combinations of sampling time points and reference levels can be selected based on knowledge about the expected arrival times of the pulses, and based on knowledge about the possible shapes of said pulses, with the result that the device can detect received pulses without requiring large amounts of hardware, in a device which has an acceptable power consumption. The communications system may be a signaling system, or a radar or positioning system.

Abstract: Data is received with a transceiver circuit with a receiver branch (14) that comprises a notch filter (140) and a digital Fourier transformer (146). Furthermore the transceiver circuit has a transmitter branch (16) comprising an inverse digital Fourier transformer (160). Prior to reception the transceiver circuit is switched to a calibration mode, wherein an output of the transmitter branch (16) is coupled to an input of the notch filter (140). The inverse digital Fourier transformer (160) of the transmitter is used to compute an inverse transform of a spectrum with a frequency component at a selected position. A signal derived from the inverse transform is applied to an input of the notch filter (140) in the calibration mode. The digital Fourier transformer (146) is used to Fourier transform an output signal of the notch filter (140). A control setting of the notch filter to suppress the frequency component from an output of the digital Fourier transformer (146) is determined.

Abstract: A frequency hopping receiver circuit has a frequency converter (12) and a hopping control circuit (14) coupled to the frequency converter (12), and configured to control frequency hopping of the received frequency, by controlling changes in frequency shift applied by the frequency converter (12). The frequency change is applied in combination with a temporary reduction in conversion gain of the frequency converter (12) during the change in frequency shift. The frequency converter may contain a mixer (122), a local oscillator circuit (120) and a controllable amplifier (124) coupled between the input of the frequency converter (12) and the mixer (122) or between the mixer (122) and the output of the frequency converter (12), or between the local oscillator circuit (120) and the local oscillator input of the mixer (122).

Abstract: A power supply arrangement is for supplying power to a chip core. A dc-dc converter arrangement is used both for a wake-up state of the core in preparation for an active state, and for a shut down charge recycling state in which the core supplies charge to the dc-dc converter. Thus, the dc-dc converter arrangement functions both to control powering on of the core in an efficient manner and the powering down of the core to implement charge recycling.

Abstract: A communication apparatus (200) has a calibration mode in which a signal is passed through circuitry (30, 80) of the apparatus, and a controller (160) measures the response of the circuitry (30, 80) to the signal and adjusts the circuitry (30, 80) to improve performance. The signal used for calibration has a wider bandwidth than the bandwidth of signals used for transmission. The wider bandwidth may be provided by reconfiguring a digital filter (20) from low-pass to high-pass.

Abstract: In a receiver architecture, for example for use in receiving pulses in an Ultra Wideband system, a received signal is applied to a mixer, together with pulses which correspond to expected received pulses. The mixer output is applied to a block, which can be configured either as an integrator or as a filter. When no pulses are being received, this block is configured as a filter, allowing it to lock quickly to any new sequence of pulses, while, when the system has locked to a sequence of pulses, the block is configured as an integrator, so that an improved signal-noise ratio can be achieved.

Abstract: In a receiver architecture, for example for use in receiving pulses in an Ultra Wideband system, a received signal is applied to a mixer, together with pulses which correspond to expected received pulses. The mixer output is applied to a block, which can be configured either as an integrator or as a filter. When no pulses are being received, this block is configured as a filter, allowing it to lock quickly to any new sequence of pulses, while, when the system has locked to a sequence of pulses, the block is configured as an integrator, so that an improved signal-noise ratio can be achieved.

Abstract: A receiver is suitable for use in a wireless communications system, which is subject to interference from interfering signals having much narrower bandwidths than the wanted signal. In the receiver, an interfering signal is detected in the frequency domain and moreover, the cancellation also takes place in the frequency domain. Detection and cancellation in the frequency domain also provides a way of estimating the magnitude of the interfering signal, and hence also allows the wanted signal, at the frequency of the interfering signal, to be estimated.

Abstract: Pulses are detected in a communications receiver by programming each of a plurality of comparators (44a, 44b, . . . , 44n) with a sampling time point selected from a plurality of sampling time points (58, 60) and with a reference level selected from a plurality of reference levels (54, 56). The received signal is applied to each of the comparators such that each of the comparators produces a respective output signal based on a comparison between the received signal level and the selected reference level at the selected sampling time point. The combinations of sampling time points and reference levels can be selected based on knowledge about the expected arrival times of the pulses, and based on knowledge about the possible shapes of said pulses, with the result that the device can detect received pulses without requiring large amounts of hardware, in a device which has an acceptable power consumption. The communications system may be a signaling system, or a radar or positioning system.