Abstract: A failure of a first memory access operation is detected at a memory device. Responsive to the detection, a first error control operation and a second error control operation are performed. In response to a determination that the second error control operation has remedied the failed first memory access operation, the second error control operation is associated with a second priority which is higher than a first priority associated with the first error control operation.

Abstract: A processing device in a memory sub-system identifies a plurality of word lines at a first portion of a memory device, determines a respective error rate for each of the plurality of word lines, and determines that a first error rate of a first word line of the plurality of word lines and a second error rate of a second word line of the plurality of word lines satisfy a first threshold condition pertaining to an error rate threshold. The processing device further identifies a third word line of the plurality of word lines that is proximate to the first word line and the second word line and relocates data stored at the third word line to a second portion of the memory device, wherein the second portion of the memory device is associated with a lower read latency than the first portion of the memory device.

Abstract: A processing device, operatively coupled with the memory device, is configured to determine a first error rate associated a first set of pages of a plurality of pages of a data unit of a memory device, and a second error rate associated with a second set of pages of the plurality of pages of the data unit, determine a first pattern of error rate change for the data unit based on the first error rate and the second error rate, and responsive to determining that the first pattern of error rate change corresponds to a predetermined second pattern of error rate change, perform an action pertaining to defect remediation with respect to the data unit.

Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on at least one of a physical block or a plurality of physical blocks of a memory device, wherein the counter is associated with the physical block or the plurality of physical blocks depending on an age of data stored on the physical block. The processing device further determines whether a value of the counter satisfies a first threshold criterion pertaining to the number of read operations performed, and responsive to the value of the counter satisfying the first threshold criterion, performs a data integrity scan to determine a first error rate.

Abstract: Read operations can be performed to read data stored at a data block. Parameters reflective of a separation between a pair of programming distributions associated with the data block can be determined based on the plurality of read operations. A read request to read the data stored at the data block can be received. In response to receiving the read request, a read operation can be performed to read the data stored at the data block based on the parameters that are reflective of the separation between the pair of programming distributions associated with the data block.

Abstract: A processing device, operatively coupled with the memory device, is configured to perform an operation on a page of a plurality of pages of a data unit of the memory device to modify data on the page. The processing device also determines a first operation execution time of the page upon performing the operation on the page of the data unit. The processing device further determines whether the first operation execution time satisfies a condition that is based on a predetermined second operation execution time, the predetermined second operation execution time is indicative of lack of defect in at least one other data unit. Lastly, responsive to determining that the first operation execution time satisfies the condition, the processing device performs a scan operation of at least a subset of the plurality of pages of the data unit to decide whether the data unit has a defect.

Abstract: A memory access operation can be determined to have failed. A determination can be made as to whether a performance of a first error control operation has remedied the failure of the memory access operation. In response to determining that the first error control operation has remedied the failure of the memory access operation, an order of a performance of one or more prioritized error control operations of the plurality of prioritized error control operations can be changed for a subsequent memory access operation that has failed based on the first error control operation that has remedied the failure.

Abstract: A first data block of multiple data blocks is identified in a first portion of the memory component, the first data block being identified based on a read count associated with the first data block satisfies a first threshold criterion. A determination is made as to whether a second portion of the memory component has an amount of unused storage to store data stored at the first data block, wherein the second portion of the memory component is associated with a lower read latency than the first portion. In response to determining that the second portion of the memory component has the amount of unused storage to store the data stored at the first data block, data stored at the first data block in the first portion of the memory component is relocated to a second data block in the second portion of the memory component. An error rate is evaluated on each word line in the first data block.

Abstract: An indication to perform a write operation at a memory component can be received. A voltage pulse can be applied to a destination block of the memory component to store data of the write operation, the voltage pulse being at a first voltage level associated with a programmed state. An erase operation for the destination block can be performed to change the voltage state of the memory cell from the programmed state to a second voltage state associated with an erased state. A write operation can be performed to write the data to the destination block upon changing the voltage state of the memory cell to the second voltage state.

Abstract: An indication of an initialization of power to a memory device is received. Responsive to receiving the indication of the initialization of power to the memory device, whether a status indicator associated with a written page of the memory device can be read is determined. Responsive to determining that the status indicator cannot be read, a programming of data to the memory device did not complete based on a prior loss of power to the memory device is determined.

Abstract: A processing device, operatively coupled with the memory device, is configured to perform a first program erase cycle (PEC) on a data unit of a memory device, wherein performing the first PEC comprises scanning a first set of pages of a plurality of pages of the data unit to determine a first error rate. The processing device also determines a first pattern of error rate change for the data unit based on the first error rate and a second error rate. The processing device then compares the first pattern of error rate change for the data unit with a predetermined pattern of error rate that is indicative of a defect. Responsive to determining that the first pattern of error rate change corresponds to the predetermined pattern of error rate change, the processing device performs an action pertaining to defect remediation with respect to the data unit.

Abstract: A request to perform a secure erase operation for a memory component can be received. A voltage level that is applied to unselected wordlines of the memory component during a read operation can be determined. A voltage pulse can be applied to at least one wordline of the memory component to perform the secure erase operation.

Abstract: A processing device in a memory system receives a request to erase a data block of a memory device, determines a number of program/erase cycles performed on the data block, and performs an erase operation to erase the data block. The processing device further determines that the number of program/erase cycles performed on the data block satisfies a scan threshold condition and performs a first threshold voltage integrity scan on the data block to determine a first error rate associated with a current threshold voltage of at least one select gate device of the data block. Responsive to the first error rate associated with the current threshold voltage of the at least one select gate device satisfying an error threshold criterion, the processing device performs a touch up operation on the at least one select gate device to adjust the current threshold voltage to the target threshold voltage.

Abstract: A processing device in a memory system determines that a first metric of a first memory unit on a first plane of a memory device satisfies a first threshold criterion. The processing device further determines whether a second metric of a second memory unit on a second plane of the memory device satisfies a second threshold criterion, wherein the second block is associated with the first block, and wherein the second threshold criterion is lower than the first threshold criterion. Responsive to the second metric satisfying the second threshold criterion, the processing device performs a multi-plane data integrity operation to determine a first reliability statistic for the first memory unit and a second reliability statistic for the second memory unit in parallel.

Abstract: Host data to be written to a storage area including a set of multiple planes of a memory device is received. A first parity generation operation based on a portion of the set of multiple planes of the host data to generate a set of multi-plane parity data is executed. The set of multi-plane parity data is stored in in a cache memory of a controller of a memory sub-system. A second parity generation operation based on the set of the multiple planes of the host data to generate a set of multi-page parity data is executed. The set of multi-page parity data in the cache memory of the controller of the memory sub-system is stored. A data recovery operation is performed based on the set of multi-plane parity data and the set of multi-page parity data.

Abstract: A request to perform a write operation at a memory component can be received. A destination block of the memory component to store data of the write operation can be determined. A voltage pulse can be applied to the destination block that places a memory cell of the destination block at a voltage level associated with a high voltage state. Responsive to applying the voltage pulse to the destination block, an erase operation for the destination block can be performed to change the voltage level of the memory cell from the high voltage state to a low voltage state. A write operation can be performed to write the data to the destination block that is at the low voltage state.

Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on at least one of a physical block or a plurality of physical blocks of a memory device, wherein the counter is associated with the physical block or the plurality of physical blocks depending on an age of data stored on the physical block. The processing device further determines whether a value of the counter satisfies a first threshold criterion pertaining to the number of read operations performed, and responsive to the value of the counter satisfying the first threshold criterion, performs a data integrity scan to determine a first error rate.

Abstract: A processing device in a memory system maintains a counter to track a number of read operations performed on a data block of a memory device and determines that the number of read operations performed on the data block satisfies a first threshold criterion. The processing device further determines whether a number of scan operations performed on the data block satisfies a scan threshold criterion. Responsive to the number of scan operations performed on the data block satisfying the scan threshold criterion, the processing device performs a first data integrity scan to determine one or more first error rates for the data block, each of the one or more first error rates corresponding to a first set of wordlines of the data block, the first set comprising first alternating pairs of adjacent wordlines.

Abstract: A set of memory cells in a data block of a memory component is sampled. A distribution statistic is generated for the data block based on a reliability statistic for each of the set of sampled memory cells. A determination is made based on the distribution statistic of whether the read disturb stress is uniformly or non-uniformly distributed across the data block. In response to a determination that the read disturb stress is non-uniformly distributed across the data block, a first subset of the data block is relocated to another data block of the memory component. The first subset of the data block is associated with a higher concentration of read disturb stress than other subsets of the data block.

Abstract: Read operations can be performed to read data stored at a data block. Parameters reflective of a separation between a pair of programming distributions associated with the data block can be determined based on the plurality of read operations. A read request to read the data stored at the data block can be received. In response to receiving the read request, a read operation can be performed to read the data stored at the data block based on the parameters that are reflective of the separation between the pair of programming distributions associated with the data block.