Abstract: A system may include a primary memory, a secondary memory, and a processor that may be communicatively coupled to one another. The processor may be configured to control data packet transmissions received via an input to the primary memory and the secondary memory. Further, the processor may be configured to monitor a current buffering level of the primary memory; and compare the first current buffering level to a first buffering threshold. The first buffering threshold may be indicative of a buffering capacity difference between a first buffering capacity of the primary memory and a second buffering capacity of the secondary memory. In response to determining that the current buffering level is equal to or greater than the first buffering threshold, pause the data packet transmissions via the input to the to the primary memory and the secondary memory.