Patents by Inventor Harish Venkatappa

Harish Venkatappa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9710578
    Abstract: Various techniques are provided to configure embedded hardware resources of a programmable logic device (PLD). In one example, a method includes receiving configuration information for a plurality of hardware modules of an embedded hardware block of a PLD. The configuration information is received from a user of a computer system external to the PLD. The method also includes generating a plurality of models of the hardware block. The method also includes merging the generated models into a combined model of the hardware block. The combined model includes the configuration information received for the hardware modules of the hardware block. Related systems and additional techniques are also provided.
    Type: Grant
    Filed: October 14, 2013
    Date of Patent: July 18, 2017
    Assignee: Lattice Semiconductor Corporation
    Inventors: Debaprosad Dutt, Jamie Freed, Harish Venkatappa, Pradeep Lenka, Minghao Ni
  • Publication number: 20140109031
    Abstract: Various techniques are provided to configure embedded hardware resources of a programmable logic device (PLD). In one example, a method includes receiving configuration information for a plurality of hardware modules of an embedded hardware block of a PLD. The configuration information is received from a user of a computer system external to the PLD. The method also includes generating a plurality of models of the hardware block. The method also includes merging the generated models into a combined model of the hardware block. The combined model includes the configuration information received for the hardware modules of the hardware block. Related systems and additional techniques are also provided.
    Type: Application
    Filed: October 14, 2013
    Publication date: April 17, 2014
    Applicant: Lattice Semiconductor Corporation
    Inventors: Debaprosad Dutt, Jamie Freed, Harish Venkatappa, Pradeep Lenka, Minghao Ni
  • Patent number: 7681160
    Abstract: Various techniques are provided to selectively collapse connections. In one example, a computer readable medium includes a computer program for performing a method of selectively collapsing connections between a plurality of LUTs. The method includes performing a first timing analysis to determine a timing slack value for each connection and determine a number of timing paths using each connection. The method also includes calculating a weight for each connection based on at least the timing slack value and the number of timing paths. The method further includes comparing the connections associated with a first one weight interval with collapsing criteria, wherein the first weight interval includes weights larger than weights of the remaining weight intervals. The method also includes collapsing the connections associated with the first weight interval that satisfy the collapsing criteria, and selectively repeating the comparing and collapsing for connections associated with remaining weight intervals.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: March 16, 2010
    Assignee: Lattice Semiconductor Corporation
    Inventors: Gilles Bosco, Issak Veytsman, Harish Venkatappa