Abstract: The present invention is directed to a device comprising an epitaxial structure comprising a superlattice structure having an uppermost 2DxG channel, a lowermost 2DxG channel and at least one intermediate 2DxG channel located between the uppermost and lowermost 2DxG channels, source and drain electrodes operatively connected to each of the 2DxG channels, and a plurality of trenches located between the source and drain electrodes. Each trench has length, width and depth dimensions defining a first sidewall, a second sidewall and a bottom located therebetween, the bottom of each trench being at or below the lowermost 2DxG channel. A crenelated gate electrode is located over the uppermost 2DxG channel, the gate electrode being located within each of the trenches such that the bottom surface of the gate electrode is in juxtaposition with the first sidewall surface, the bottom surface and the second sidewall surface of each of said trenches.

Abstract: The present invention is directed to a device comprising an epitaxial structure comprising a superlattice structure having an uppermost 2DxG channel, a lowermost 2DxG channel and at least one intermediate 2DxG channel located between the uppermost and lowermost 2DxG channels, source and drain electrodes operatively connected to each of the 2DxG channels, and a plurality of trenches located between the source and drain electrodes. Each trench has length, width and depth dimensions defining a first sidewall, a second sidewall and a bottom located therebetween, the bottom of each trench being at or below the lowermost 2DxG channel. A crenelated gate electrode is located over the uppermost 2DxG channel, the gate electrode being located within each of the trenches such that the bottom surface of the gate electrode is in juxtaposition with the first sidewall surface, the bottom surface and the second sidewall surface of each of said trenches.

Abstract: A method is provided for forming a through substrate via in a compound semiconductor having a transistor on a front side of the substrate. The method comprises forming a protective stop pad over a contact area on the front side of the substrate, forming a contact pad overlying the protective stop pad, such that the contact pad is in contact with a terminal of the transistor and plasma etching a backside of the substrate to form a contact coupling via to the protective stop pad. The method further comprises performing a chemical wet etch to remove the protective stop pad and depositing a conductive contact layer in the contact coupling via to provide a conductive contact to the contact pad.

Abstract: A method is provided for forming a through substrate via in a compound semiconductor having a transistor on a front side of the substrate. The method comprises forming a protective stop pad over a contact area on the front side of the substrate, forming a contact pad overlying the protective stop pad, such that the contact pad is in contact with a terminal of the transistor and plasma etching a backside of the substrate to form a contact coupling via to the protective stop pad. The method further comprises performing a chemical wet etch to remove the protective stop pad and depositing a conductive contact layer in the contact coupling via to provide a conductive contact to the contact pad.

Abstract: A high Q monolithic metal-insulator-metal (MIM) capacitor utilizing a single crystal dielectric material. A dielectric membrane is epitaxially grown on a substrate. The membrane acts as an etch-stop when a backside etch is used to form a cavity in the substrate, resulting in a single crystal dielectric membrane spanning the cavity. Electrodes are formed on opposite surfaces of the membrane at the cavity location. For a shunt capacitor application, the bottom electrode is connected to the backside substrate metallization. For a series capacitor application, the bottom electrode is isolated from the backside metallization, but is connected to the topside circuitry through a via formed in the membrane. The membrane may consist of two dielectric layers, where the first layer is an etchstop material. In one embodiment the substrate and second dielectric layer are gallium arsenide and the first dielectric layer is aluminum gallium arsenide.