Abstract: Disclosed is a method for making a semiconductor pressure transducer structure in CMOS integrated circuits. The method includes patterning a first metallization layer that lies over an first oxide layer to produce a first patterned metallization layer that is not in electrical contact with a substrate. Forming a tungsten plug in a second oxide layer that overlies the first patterned metallization layer, such that the tungsten plug is in electrical contact with the first patterned metallization layer. Patterning a second metallization layer that overlies the first patterned metallization layer and the tungsten plug to produce a second patterned metallization layer. The patterning of the second metallization layer is configured to prevent the second patterned metallization layer from completely overlying the tungsten plug. The method further includes submerging the pressure transducer structure in a basic solution having a pH level that is greater than about 7.

Abstract: Disclosed is a semiconductor diode structure, and method for making semiconductor diode structures for suppressing transistor gate oxide plasma charging damage. The semiconductor diode structure includes a shallow trench isolation region that is configured to isolate an active region of a semiconductor substrate. A doped polysilicon electrode having a first end and a second end. The doped polysilicon electrode is defined in the shallow trench isolation region and the first end is configured to be in electrical contact with the semiconductor substrate. The diode structure further includes a polysilicon gate that has an underlying gate oxide. The polysilicon gate is defined over the active region and extends over part of the shallow trench isolation region so as to make electrical interconnection between the polysilicon gate and the second end of the doped polysilicon electrode.

Abstract: A semiconductor transistor includes a modified gate structure defined over a substrate, such structure includes a polysilicon inner region having a top surface gate length and a bottom surface gate length disposed over the substrate. The bottom surface gate length has a modified gate length value that is shorter than a gate length value of the top surface gate length. A spacer defines a border around the polysilicon inner region, the border is configured to define the modified gate length value. The modified gate length value is less than the limit of the photolithography that is used to manufacture the transistor structure. The value (in microns) of the modified gate length LG is less than the lithography-limited gate length. Additionally, after the at least one spacer is defined, and thus, after the modified gate length is defined, a source/drain extension is located substantially below the spacer that defines the border around the polysilicon inner region.

Abstract: Disclosed is a method for making a programmable structure on a semiconductor substrate. The semiconductor structure has a first dielectric layer. The method includes plasma patterning a first metallization layer over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer. Each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over each of the tungsten plugs is not covered by the second metallization layer. Applying a programming electron dose to a portion of the second metallization layer.

Abstract: Disclosed is a method for making reliable interconnect structures on a semiconductor wafer having a first dielectric layer. The method includes plasma patterning a first metallization layer over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer, such that each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over at least one of the tungsten plugs is not covered by the second metallization layer and a positive charge is built-up on at least part of the second metallization layer.

Abstract: Disclosed is a method for making reliable interconnect structures on a semiconductor substrate having a first dielectric layer. The method includes plasma patterning a first metallization layer that lies over the first dielectric layer. Forming a second dielectric layer over the first metallization layer and the first dielectric layer. Forming a plurality of tungsten plugs in the second dielectric layer, such that each of the plurality of tungsten plugs are in electrical contact with the first metallization layer. Plasma patterning a second metallization layer over the second dielectric layer and the plurality of tungsten plugs, such that at least a gap over at least one of the tungsten plugs is not covered by the second metallization layer and a positive charge is built-up on at least part of the second metallization layer. The method further includes contacting the second metallization layer with a conductive liquid that is electrically grounded.

Abstract: Disclosed is a semiconductor diode structure, and method for making semiconductor diode structures for suppressing transistor gate oxide plasma charging damage. The semiconductor diode structure includes a shallow trench isolation region that is configured to isolate an active region of a semiconductor substrate. A doped polysilicon electrode having a first end and a second end. The doped polysilicon electrode is defined in the shallow trench isolation region and the first end is configured to be in electrical contact with the semiconductor substrate. The diode structure further includes a polysilicon gate that has an underlying gate oxide. The polysilicon gate is defined over the active region and extends over part of the shallow trench isolation region so as to make electrical interconnection between the polysilicon gate and the second end of the doped polysilicon electrode.

Abstract: Disclosed is a method for making a semiconductor pressure transducer structure in CMOS integrated circuits. The method includes patterning a first metallization layer that lies over an first oxide layer to produce a first patterned metallization layer that is not in electrical contact with a substrate. Forming a tungsten plug in a second oxide layer that overlies the first patterned metallization layer, such that the tungsten plug is in electrical contact with the first patterned metallization layer. Patterning a second metallization layer that overlies the first patterned metallization layer and the tungsten plug to produce a second patterned metallization layer. The patterning of the second metallization layer is configured to prevent the second patterned metallization layer from completely overlying the tungsten plug. The method further includes submerging the pressure transducer structure in a basic solution having a pH level that is greater than about 7.

Abstract: A resistive load structure and method for making a resistive load structure for an integrated circuit includes the use of an amorphous silicon "antifuse" material. The resistive load structure can be used in an SRAM cell to provide a load to counteract charge leakage at the drains of two pull-down transistors and two pass transistors of the SRAM cell. The resistive load structure is advantageously formed by depositing an amorphous silicon pad over a conductive via, and the resistance of the resistive load structure is controlled by adjusting the thickness of the amorphous silicon pad and varying the diameter of the underlying conductive via.

Abstract: Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

Abstract: Disclosed is a semiconductor fuse structure having a low power programming threshold and anti-reverse engineering characteristics. The fuse structure includes a substrate having a field oxide region. A polysilicon strip that has an increased dopant concentration region lies over the field oxide region. The fuse structure further includes a silicided metallization layer having first and second regions lying over the polysilicon strip. The first region has a first thickness, and the second region has a second thickness that is less than the first thickness and is positioned substantially over the increased dopant concentration region of the polysilicon strip. Preferably, the first region of the silicided metallization layer has a first side and a second side located on opposite sides of the second region, and the resulting fuse structure is substantially rectangular in shape. Therefore, the semiconductor fuse structure can be programmed by breaking the second region.

Abstract: A resistive load structure and method for making a resistive load structure for an integrated circuit includes the use of an amorphous silicon "antifuse" material. The resistive load structure can be used in an SRAM cell to provide a load to counteract charge leakage at the drains of two pull-down transistors and two pass transistors of the SRAM cell. The resistive load structure is advantageously formed by depositing an amorphous silicon pad over a conductive via, and the resistance of the resistive load structure is controlled by adjusting the thickness of the amorphous silicon pad and varying the diameter of the underlying conductive via.