Abstract: This application discloses a computing system implementing a synthesis tool to synthesize a circuit design of an electronic system into a gate-level netlist having a logical hierarchy, utilize the gate-level netlist to generate a physical representation of the circuit design, and partition the circuit design into sub-designs based on the physical representation of the circuit design. The computing system can generate physical modules having self-contained physical definitions from the sub-designs, and reassemble the physical modules into a gate-level netlist having a physical hierarchy corresponding to the partitions of the circuit design. The computing system also can regroup modules in the circuit design based on the physical hierarchy, modify the circuit design to have the physical hierarchy based on the regrouped modules, and synthesize the modified circuit design into the gate-level netlist having the physical hierarchy.