Abstract: The invention relates to a voltage regulator circuit arrangement comprising a voltage regulator for generating an out-put voltage in dependence of a reference signal, characterized in that a reference signal generation circuit is provided for generating said reference signal comprising a plurality of inputs connected to internal terminals, whereby a sub-set of said plurality internal terminals is connected to an external terminal.

Abstract: The communication bus system comprises a plurality of node circuits (10a-d) and a relay circuit (12, 14, 16) coupling the node circuits (10a-d). The relay circuit (12, 14, 16) has a transceiver circuit (124, 164) for relaying messages (21) between the node circuits (10a-d) in a normal mode. The transceiver circuit (124, 164) is powered down in a sleep mode. A detector circuit (120, 160) detects an incoming message (41) when the relay circuit (12, 14, 16) is in a sleep mode. A mode control circuit (122, 162) powers up the transceiver (124, 164) in response to detection of an incoming message (21). Steps are taken that ensure, in the normal mode, that messages (21) will not be relayed in unreadable form. The mode control circuit (122, 162) is arranged to cause the transceiver (124, 164) to relay a remainder (25) of the incoming message (21) after power up.