Patents by Inventor Harmandeep Singh

Harmandeep Singh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240411646
    Abstract: Methods, systems, and devices for data management are described. A snapshot chain may include a full snapshot of a data block and incremental snapshots including changes to partitions of the data block since the full snapshot. A snapshot in the snapshot chain may be marked for deletion. A data management system (DMS) may perform an operation to convert a most recent incremental snapshot to a full snapshot. As part of the operation, the DMS may write, from snapshots in the snapshot chain that include data in different partitions of the data block, the data to more recent snapshots that satisfy conditions. The conditions may include the more recent snapshot not being marked for deletion and being a most recent snapshot in the snapshot chain that has an empty data set in the respective partition. As part of the operation, the DMS may delete snapshots that are marked for deletion.
    Type: Application
    Filed: June 8, 2023
    Publication date: December 12, 2024
    Inventor: Harmandeep Singh
  • Patent number: 11023636
    Abstract: Disclosed are methods, systems, and articles of manufacture for characterizing an electronic design with a susceptibility window. These techniques identify a set of multiple aggressors in an electronic design and determine, at a susceptibility window module stored in memory and executing in conjunction with a microprocessor of a computing node, a susceptibility window for an internal node of a victim and a timing window for the set of multiple aggressors in the electronic design. These techniques further determine a subset having at least one aggressor using at least the susceptibility window of the victim and the timing window for the set of multiple aggressors, and determine whether a glitch in the electronic design causes a violation at the internal node of the electronic design based at least in part upon the timing window and the susceptibility.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: June 1, 2021
    Assignee: Cadence Design Systems, Inc.
    Inventors: Igor Keller, Ratnakar Goyal, Manuj Verma, Harmandeep Singh