Abstract: A programmable logic circuit such as a finite state machine is provided that is configured to determine a memory array power-up sequence from a configuration signal to successively enable each memory array. A delay circuit triggers an initial memory bank in each enabled memory array to power-up without a delay. The delay circuit then counts responsive to a clock to determine a delay between a successive triggering of remaining memory banks in each enabled memory array to power-up.

Abstract: In some aspects, a method for adjusting an operating frequency of a memory controller is provided, wherein a graphics processing unit (GPU) accesses a memory via the memory controller. The method includes monitoring activity of the GPU to determine an active time of the GPU, comparing the determined active time with an active threshold, and, if the determined active time is greater than the active threshold, increasing the operating frequency of the memory controller.

Abstract: A programmable logic circuit such as a finite state machine is provided that is configured to determine a memory array power-up sequence from a configuration signal to successively enable each memory array. A delay circuit triggers an initial memory bank in each enabled memory array to power-up without a delay. The delay circuit then counts responsive to a clock to determine a delay between a successive triggering of remaining memory banks in each enabled memory array to power-up.

Abstract: In some aspects, a method for adjusting an operating frequency of a memory controller is provided, wherein a graphics processing unit (GPU) accesses a memory via the memory controller. The method includes monitoring activity of the GPU to determine an active time of the GPU, comparing the determined active time with an active threshold, and, if the determined active time is greater than the active threshold, increasing the operating frequency of the memory controller.

Abstract: Described is an apparatus comprising: a voltage level detector to monitor a first power supply node; and a voltage level protector, coupled to the voltage level detector, to protect the voltage level detector from receiving a power supply on the first power supply node above a pre-defined threshold voltage. Described is also a voltage level protector to protect a first power supply node from receiving a power supply above a pre-defined threshold voltage, the voltage level protector comprising: a first p-type device coupled to a second power supply node, the second power supply node to receive a power supply higher than the power supply on the first power supply node; and a second p-type device coupled in series to the first p-type device, the second p-type further coupled to the first power supply node, which is for coupling to a voltage level detector.

Abstract: Systems and methods for optimizing a memory rail voltage are disclosed. The system may comprise a plurality of sensor cells, each sensor cell comprising at least one bitcell replica having a predefined data retention voltage higher than a data retention voltage of a similar memory bit cell. The sensor cells may be configured to provide an output based on a sensor rail voltage higher than the predefined data retention voltage. The system may further comprise a controller operably coupled to a power management circuit and configured to adjust the memory rail and the sensor rail voltages. The controller may be further configured to compare an expected value to the sensor indication. The controller may decrease the sensor rail voltage and the memory rail voltage based on the indication until a sensor indicates a bitcell replica has failed, indicating an optimum memory rail voltage has been reached.

Abstract: Described is an apparatus comprising: a voltage level detector to monitor a first power supply node; and a voltage level protector, coupled to the voltage level detector, to protect the voltage level detector from receiving a power supply on the first power supply node above a pre-defined threshold voltage. Described is also a voltage level protector to protect a first power supply node from receiving a power supply above a pre-defined threshold voltage, the voltage level protector comprising: a first p-type device coupled to a second power supply node, the second power supply node to receive a power supply higher than the power supply on the first power supply node; and a second p-type device coupled in series to the first p-type device, the second p-type further coupled to the first power supply node, which is for coupling to a voltage level detector.

Abstract: A static pulse bus circuit and method having dynamic power supply rail selection reduces static and dynamic power consumption over that of static pulse bus designs with fixed power supply rail voltages. Every other (even) bus repeater is operated with a selectable power supply rail voltage that is selected in conformity with a state of the input signal of the bus repeater. The odd bus repeaters are operated from the lower of the selectable power supply voltages supplied to the even repeaters. The odd bus repeaters may also be operated from a selectable power supply rail voltage opposite the selectable-voltage power supply rail provided to the even bus repeaters, in which case the opposing rail of the even bus repeaters is set to the higher of the voltages selectable in the odd bus repeaters.

Abstract: An improved process for the manufacture of 1-[[[(1R)-1-[3-[(1E)-2-(7-chloro-2-quinolinyl)ethenyl]phenyl]-3-[2-(1-hydroxy-1-methylethyl)phenyl]propyl]thio]methyl]cyclopropane acetic acid, sodium salt [montelukast sodium(I)]. It consists of converting a vital intermediate 1-(mercaptomethyl)-cyclopropane acetic acid of formula IX, to a quaternary ammonium salt of formula X, using a suitable base in a suitable solvent at 0° C. to 50° C. followed by monometalation to provide an intermediate of formula XI and subsequent condensation of XI with 2-[2-[3-(S)-[3-[2-(7-chloro-2-quinolinyl)-ethenyl]phenyl]-3-methanesulphonyloxypropyl]phenyl]-2-propanol at 0 to ?50° C.

Abstract: Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature.

Abstract: A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.

Abstract: A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.

Abstract: A method and system for calibration of multi-metric sensitive delay measurement circuits provides for reduction of process-dependent variation in delays and their sensitivities to circuit metrics. A process corner for the delay circuit(s) is determined from at least one delay measurement for which the variation of delay due to process variation is previously characterized. The delay measurement(s) is made at a known temperature(s), power supply voltage(s) and known values of any other environmental metric which the delay circuit is designed to measure. Coefficients for delay versus circuit metrics are then determined from the established process corner, so that computation of circuit metric values from the delay measurements have improved accuracy and reduced variation due to the circuit-to-circuit and/or die-to-die process variation of the delay circuits.

Abstract: Correction of delay-based metric measurements using delay circuits having differing metric sensitivities provides improved accuracy for environmental and other circuit metric measurements that used delay lines. A delay line measurement, which may be a one-shot measurement or a ring oscillator frequency measurement is performed either simultaneously or sequentially using at least two delay lines that have differing sensitivities to a particular metric under measurement. A correction circuit or algorithm uses the measured delays or ring oscillator frequencies and corrects at least one of the metric measurements determined from one of the delays or ring oscillator frequencies in conformity with the other delay or ring oscillator frequency. The delays may be inverter chains, with one chain having a higher sensitivity to supply voltage than the other delay chain, with the other delay chain having a higher sensitivity to temperature.

Abstract: A static pulse bus circuit and method having dynamic power supply rail selection reduces static and dynamic power consumption over that of static pulse bus designs with fixed power supply rail voltages. Every other (even) bus repeater is operated with a selectable power supply rail voltage that is selected in conformity with a state of the input signal of the bus repeater. The odd bus repeaters are operated from the lower of the selectable power supply voltages supplied to the even repeaters. The odd bus repeaters may also be operated from a selectable power supply rail voltage opposite the selectable-voltage power supply rail provided to the even bus repeaters, in which case the opposing rail of the even bus repeaters is set to the higher of the voltages selectable in the odd bus repeaters.

Abstract: A dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control reduces power consumption of processors and other systems incorporating dynamic circuits. The power control signal may be a delayed version of the logic clock and turns on the output inverter foot device after the dynamic node has had sufficient time to evaluate, providing a fast evaluate time and reducing leakage through the inverter input when the foot device is off. Alternatively, a coarsely timed static power control signal may be used to control the inverter foot devices. The drains of the inverter foot devices can be commonly connected across multiple circuits, reducing the foot device total area.

Abstract: A dynamic logic circuit incorporating reduced leakage state-retaining devices reduces power consumption of processors and other systems incorporating dynamic circuits. A keeper circuit provides a low leakage retention of the state of the output stage of the dynamic circuit so that an output circuit foot device can be disabled except when required for a transition in the output of the dynamic circuit. The keeper circuit includes a transistor having a smaller area than a corresponding transistor in the output circuit, thus reducing leakage through the gate of the output circuit when the keeper circuit is holding the output and the output circuit foot device is disabled. A self-clocked control of the output circuit foot device can be provided via a delayed version of the dynamic logic gate output, or may be provided by an external control circuit that generates a delayed version of the precharge clock or a multi-cycle signal.

Abstract: A multi-threshold complementary metal-oxide semiconductor (MTCMO) bus circuit reduces bus power consumption via a reduced circuit leakage standby and pulsed control of standby mode so that the advantages of MTCMOS repeater design are realized in dynamic operation. A pulse generator pulses the high-threshold voltage power supply rail standby switching devices in response to changes detected at the bus circuit inputs. The delay penalty associated with leaving the standby mode is overcome by reducing cross-talk induced delay via a cross-talk noise minimization encoding and decoding scheme. A subgroup of bus wires is encoded and decoded, simplifying the encoding, decoding and change detection logic and results in the bus subgroup being taken out of standby mode only when changes occur in one or more of the subgroup inputs, further reducing the power consumption of the overall bus circuit.