Patents by Inventor Harmeet Sobti

Harmeet Sobti has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Manufacturability (DFM) cells in extreme ultra violet (EUV) technology
    Patent number: 10790272
    Abstract: Aspects of the disclosure are directed to a circuit. In accordance with one aspect, the circuit includes a first layer, wherein the first layer includes two-dimensional (2D) shapes; a second layer coupled adjacent to the first layer through at least one via hole, wherein the second layer includes only one-dimensional (1D) shapes; a shared drain terminal; and a source terminal termination.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: September 29, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Harmeet Sobti, Mehrdad Manesh, Li-Fu Chang
  • DESIGN FOR MANUFACTURABILITY (DFM) CELLS IN EXTREME ULTRA VIOLET (EUV) TECHNOLOGY
    Publication number: 20190043850
    Abstract: Aspects of the disclosure are directed to a circuit. In accordance with one aspect, the circuit includes a first layer, wherein the first layer includes two-dimensional (2D) shapes; a second layer coupled adjacent to the first layer through at least one via hole, wherein the second layer includes only one-dimensional (1D) shapes; a shared drain terminal; and a source terminal termination.
    Type: Application
    Filed: July 30, 2018
    Publication date: February 7, 2019
    Inventors: Harmeet SOBTI, Mehrdad MANESH, Li-Fu CHANG
  • Dual-gate VDMOS device
    Patent number: 8963218
    Abstract: Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: February 24, 2015
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Harmeet Sobti, Timothy K. McGuire, David L. Snyder, Scott J. Alberhasky
  • DUAL-GATE VDMOS DEVICE
    Publication number: 20130082321
    Abstract: Semiconductor devices are described that include a dual-gate configuration. In one or more implementations, the semiconductor devices include a substrate having a first surface and a second surface. The substrate includes a first and a second body region formed proximal to the first surface. Moreover, each body region includes a source region formed therein. The substrate further includes a drain region formed proximal to the second surface and an epitaxial region that is configured to function as a drift region between the drain region and the source regions. A dual-gate is formed over the first surface of the substrate. The dual-gate includes a first gate region and a second gate region that define a gap there between to reduce the gate to drain capacitance.
    Type: Application
    Filed: September 30, 2011
    Publication date: April 4, 2013
    Applicant: Maxim Integrated Products, Inc.
    Inventors: Harmeet Sobti, Timothy K. McGuire, David L. Snyder, Scott J. Alberhasky