Patents by Inventor Harminder S. Banwait

Harminder S. Banwait has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8218650
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a video signal and macroblock data in response to decoding one or more bins on a binary signal. The second circuit may be configured to, in parallel (i) generate the binary signal in response to a bitstream signal and an initial context information and (ii) calculate subsequent context information.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: July 10, 2012
    Assignee: LSI Corporation
    Inventors: Eric C. Pearson, Harminder S. Banwait
  • Patent number: 7983343
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a video signal and macroblock data in response to decoding one or more bins on a binary signal. The second circuit may be configured to, in parallel (i) generate the binary signal in response to a bitstream signal and an initial context information and (ii) calculate subsequent context information.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: July 19, 2011
    Assignee: LSI Corporation
    Inventors: Eric C. Pearson, Harminder S. Banwait
  • Publication number: 20110150075
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a video signal and macroblock data in response to decoding one or more bins on a binary signal. The second circuit may be configured to, in parallel (i) generate the binary signal in response to a bitstream signal and an initial context information and (ii) calculate subsequent context information.
    Type: Application
    Filed: March 3, 2011
    Publication date: June 23, 2011
    Inventors: Eric C. Pearson, Harminder S. Banwait
  • Patent number: 7835441
    Abstract: An apparatus generally having a reference memory and a motion estimation circuit is disclosed. The reference memory may store reference samples used in a motion estimation of a current block beyond a boundary of a picture. The motion estimation circuit may (i) buffer the reference samples as copied from the reference memory, the reference samples as buffered residing both (a) inside the boundary and (b) inside a search window of the motion estimation, (ii) shift a sub-set of the reference samples to align with a corner of a sub-window, the sub-window being (a) completely within the search window and (b) at least partially outside of the boundary, (iii) fill an empty portion of the sub-window with copies of the reference samples within the sub-set and (iv) generate difference values by comparing the current block against the reference samples within the sub-window a plurality of times.
    Type: Grant
    Filed: January 15, 2008
    Date of Patent: November 16, 2010
    Assignee: LSI Corporation
    Inventors: Eric C. Pearson, Harminder S. Banwait, Michael D. Gallant
  • Patent number: 7463781
    Abstract: A method for controlling an arithmetic codec context is disclosed. The method may include the steps of (A) reading a current value indicating one of a first condition and a second condition corresponding to a current context of a plurality of predetermined contexts, (B) generating an input state matching (i) an initial state in response to the first condition and (ii) an output state in response to the second condition, wherein the initial state has a predetermined value and the output state has a value generated by the method before receiving the current context and (C) generating a current output state by performing an arithmetic code operation on an input signal using the input state.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: December 9, 2008
    Assignee: LSI Corporation
    Inventors: Eric C. Pearson, Harminder S. Banwait
  • Patent number: 7440500
    Abstract: An apparatus generally having a first memory and a circuit is disclosed. The first memory may be used for a motion estimation of a current block. The circuit may be configured to (i) determine if a search window for the current block is at least partially outside a boundary of a picture stored in a second memory, (ii) copy a first plurality of reference samples in the search window from the second memory to the first memory and (iii) map a plurality of reads from the first memory for a plurality of pad samples to the reference samples in the first memory, where the pad samples are determined to be outside the boundary.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: October 21, 2008
    Assignee: LSI Logic Corporation
    Inventors: Eric C. Pearson, Harminder S. Banwait, Michael D. Gallant
  • Patent number: 7397401
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate context information in response to one or more bins on a binary signal. The second circuit may be configured to generate the binary signal in response to (i) one or more input bits on a bitstream signal, and (ii) simultaneously performing in a single cycle (a) an arithmetic decode of the context information and (b) a renormalization of the context information.
    Type: Grant
    Filed: July 7, 2006
    Date of Patent: July 8, 2008
    Assignee: LSI Logic Corporation
    Inventors: Harminder S. Banwait, Eric C. Pearson, Scott F. James
  • Publication number: 20080007436
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate context information in response to one or more bins on a binary signal. The second circuit may be configured to generate the binary signal in response to (i) one or more input bits on a bitstream signal, and (ii) simultaneously performing in a single cycle (a) an arithmetic decode of the context information and (b) a renormalization of the context information.
    Type: Application
    Filed: July 7, 2006
    Publication date: January 10, 2008
    Inventors: Harminder S. Banwait, Eric C. Pearson, Scott F. James
  • Patent number: 7061410
    Abstract: An apparatus comprising a first circuit, a second circuit and an output circuit. The first circuit may be configured to generate (i) one of a first set of entropy coded input signals or a second set of entropy coded input signals and (ii) a data path signal. The second circuit may be configured to generate (i) a first set of entropy encoded output signals in response to decoding the second set of entropy coded input signals, or (ii) a second set of entropy coded output signals in response to decoding the first set of entropy coded input signals. The second circuit may provide real time decoding and encoding on a macroblock basis. The output circuit may be configured to present an output signal in response to (i) one of the first set of entropy coded output signals or the second set of entropy coded output signals and (ii) the data path signal.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: June 13, 2006
    Assignee: LSI Logic Corporation
    Inventors: Eric C. Pearson, Harminder S. Banwait